CY7C1512AV18-250BZI Cypress Semiconductor Corp, CY7C1512AV18-250BZI Datasheet - Page 9

• Manufacturer Part Number: CY7C1512AV18-250BZI
• Description: IC SRAM 72MBIT 250MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-250BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 001-06984 Rev. *B
Application Example
Truth Table
Write Cycle:
Load address on the rising edge of K clock;
input write data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock;
wait one and a half cycle; read data on C
and C rising edges.
NOP: No Operation
Standby: Clock Stopped
Notes:
2. The above application shows four QDR-II being used.
3. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
4. Device will power-up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
MASTER
ASIC)
BUS
(CPU
or
CLKIN/CLKIN#
Delayed K#
DATA OUT
[ 3, 4, 5, 6, 7, 8]
Delayed K
Source K#
DATA IN
Source K
Operation
Address
BWS#
WPS#
RPS#
Vt
[2]
R
R
R = 50οηµσ
D
A
Vt = Vddq/2
↑
represents rising edge.
Stopped
R
P
S
#
W
SRAM #1
P
S
#
L-H
L-H
L-H
K
W
B
S
#
PRELIMINARY
C C#
RPS
CQ/CQ#
X
H
X
L
K
ZQ
K#
Q
R = 250οηµσ
WPS
X
H
X
L
D(A + 0) at K(t) ↑
Q(A + 0) at C(t + 1) ↑
D = X
Q = High-Z
Previous State
D
A
R
DQ
Vt
Vt
R
P
S
#
W
SRAM #4
P
#
S
W
B
#
S
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
C C#
D(A + 1) at K(t) ↑
Q(A + 1) at C(t + 2) ↑
D = X
Q = High-Z
Previous State
CQ/CQ#
K
ZQ
K#
Q
DQ
Page 9 of 26
R = 250οηµσ
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