CY7C1512AV18-250BZI Cypress Semiconductor Corp, CY7C1512AV18-250BZI Datasheet - Page 8

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CY7C1512AV18-250BZI

Manufacturer Part Number
CY7C1512AV18-250BZI
Description
IC SRAM 72MBIT 250MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp

Specifications of CY7C1512AV18-250BZI

Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
72M (4M x 18)
Speed
250MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Part Number:
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Document #: 001-06984 Rev. *B
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1512AV18 is described in the following sections. The
same
CY7C1525AV18 and CY7C1514AV18.
Read Operations
The CY7C1512AV18 is organized internally as 2 arrays of
2Mx18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Positive Input Clock (K).
The address is latched on the rising edge of the K Clock. The
address presented to Address inputs is stored in the Read
address register. Following the next K clock rise the corre-
sponding lowest order 18-bit word of data is driven onto the
Q
quent rising edge of C, the next 18-bit data word is driven onto
the Q
rising edge of the output clock (C and C or K and K when in
single clock mode).
Synchronous internal circuitry will automatically tri-state the
outputs following the next rising edge of the Output Clocks
(C/C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the same K
clock rise, the data presented to D
into the lower 18-bit Write Data register provided BWS
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K), the address is latched and the infor-
mation presented to D
Register provided BWS
bits of data are then written into the memory array at the
specified location. When deselected, the write port will ignore
all inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1512AV18.
A write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS
data word. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1512AV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
[17:0]
[17:0]
using C as the output timing reference. On the subse-
basic
. The requested data will be valid 0.45 ns from the
0
and BWS
descriptions
[1:0]
[17:0]
1
which are sampled with each 18-bit
are both asserted active. The 36
is stored into the Write Data
apply
[17:0]
to
is latched and stored
[x:0]
CY7C1510AV18
) inputs pass
PRELIMINARY
[1:0]
are
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1512AV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Depth Expansion
The CY7C1512AV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
V
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
(C/C) of the QDR-II. In the single clock mode, CQ is generated
with respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device will behave in QDR-I mode (with one
cycle latency and a longer access time). For information refer
to the application note “DLL Considerations in QDRII/DDRII”.
DDQ
= 1.5V.The output impedance is adjusted every 1024
SS
to allow the SRAM to adjust its
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
Page 8 of 26
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