CY7C1512AV18-250BZI Cypress Semiconductor Corp, CY7C1512AV18-250BZI Datasheet - Page 22

• Manufacturer Part Number: CY7C1512AV18-250BZI
• Description: IC SRAM 72MBIT 250MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-250BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 001-06984 Rev. *B
Switching Characteristics
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
Notes:
26. These parameters are extrapolated from the input timing parameters (t
27. t
28. At any given voltage and temperature t
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
KC Var
KC lock
KC Reset
Parameter
included in the t
Cypress
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
KHKH
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Consortium
Parameter
). These parameters are only guaranteed by design and are not tested in production.
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS) 0.35
Double Data Rate Control Hold after Clock
(K/K) Rise (BWS
D
C/C Clock Rise (or K/K in Single Clock
Mode) to Data Valid
Data Output Hold after Output C/C Clock
Rise (Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
Clock (C/C) Rise to High-Z (Active to
High-Z)
Clock (C/ C) Rise to Low-Z
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
CHZ
Over the Operating Range
[X:0]
is less than t
Hold after Clock (K/K) Rise
[27, 28]
CLZ
Description
0
and t
, BWS
PRELIMINARY
CHZ
1
, BWS
less than t
KHKH
[27, 28]
[22, 23]
[26]
- 250ps, where 250ps is the internal jitter. An input jitter of 200ps (t
3
, BWS
CO
[26]
.
4
)
–0.45
–0.45
-0.30
-0.45
1024
Min. Max
0.35
0.35
0.35
1.55
1.55
250 MHz
30
–
–
–
–
–
0.45
0.45
0.30
0.45
0.20
–
–
–
–
–
–
–
–
–
–
–
–
-0.45
-0.45
-0.35
-0.45
1024
Min.
1.95
1.95
0.4
0.4
0.4
0.4
200 MHz
30
–
–
–
–
–
Max Min. Max
0.45
0.45
0.35
0.45
0.20
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
–
–
–
–
–
–
–
–
–
–
–
–
-0.50
-0.50
-0.40
-0.50
1024
2.45
2.45
0.5
0.5
0.5
0.5
167 MHz
30
–
–
–
–
–
0.50
0.50
0.40
0.50
0.20
Page 22 of 26
KC Var
–
–
–
–
–
–
–
–
–
–
–
–
) ia already
Cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback
[+] Feedback