DS1875T+ Maxim Integrated Products, DS1875T+ Datasheet

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DS1875T+

Manufacturer Part Number
DS1875T+
Description
IC SFP CTRLR/TRIPLEXER 38-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1875T+

Applications
Fiber Optics
Interface
I²C
Voltage - Supply
2.85 V ~ 3.9 V
Package / Case
*
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The DS1875 controls and monitors all functions for burst-
mode transmitters, APD receivers, and video receivers.
It also includes a power-supply controller for APD bias
generation, and provides all SFF-8472 diagnostic and
monitoring functionality. The combined solution of the
DS1875 and the MAX3643 laser driver provides APC
loop, modulation current control, and eye safety func-
tionality. Ten ADC channels monitor V
(both internal signals), and eight external monitor inputs
(MON1–MON8) that can be used to meet transmitter,
digital receiver, video receiver, and APD receiver-signal
monitoring requirements. Four total DAC outputs are
available. A PWM controller with feedback and compen-
sation pins can be used to generate the bias for an APD
or as a step-down converter. Five I/O pins allow addi-
tional monitoring and configuration.
Rev 1; 10/08
+ Denotes a lead-free/RoHS-compliant package.
T&R = Tape and reel.
* EP = Exposed pad.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
DS1875T+
DS1875T+T&R
TOP VIEW
PART
GND
GND
N.C.
N.C.
N.C.
V
BPON, GPON, or EPON Optical Triplexers
SFF, SFP, and SFP+ Transceiver Modules
APD Controller
SW
CC
*EXPOSED PAD.
32
33
34
35
36
37
38
31 30 29 28 27 26 25 24 23 22 21 20
+
1
2
________________________________________________________________ Maxim Integrated Products
3
(5mm
-40°C to +95°C
-40°C to +95°C
TEMP RANGE
4
Ordering Information
5
×
General Description
7mm
TQFN
DS1875
6
Pin Configuration
7
×
0.8mm)
8
9
Applications
PON Triplexer and SFP Controller
10 11 12
PIN-PACKAGE
38 TQFN-EP*
38 TQFN-EP*
CC
*EP
, temperature
19
18
17
16
15
14
13
MON4
MON2
MON1
MON8/D3
MON7/D2
MON6/D1
MON5/D0
♦ Meets All PON Burst-Timing Requirements for
♦ Laser Bias Controlled by APC Loop and
♦ Laser Modulation Controlled by Temperature LUT
♦ Six Total DACs: Four External, Two Internal
♦ Two 8-Bit DACs, One of Which is Optionally
♦ Internal 8-Bit DAC Controlled by a Temperature-
♦ PWM Controller
♦ Boost or Buck Mode
♦ Boost Mode: Uses Optional External
♦ 131kHz, 262kHz, 525kHz, or 1050kHz Selectable-
♦ APD Overcurrent Protection Using Optional Fast
♦ 10 Analog Monitor Channels: Temperature, V
♦ Internal, Factory-Calibrated Temperature Sensor
♦ RSSI with 29dB Electrical Dynamic
♦ Five I/O Pins for Additional Control and
♦ Comprehensive Fault-Measurement System with
♦ Two-Level Password Access to Protect
♦ 120 Bytes of Password-1 Protected Memory
♦ 128 Bytes of Password-2 Protected Memory in
♦ 256 Additional Bytes Located at A0h Slave
♦ I
♦ 2.85V to 3.9V Operating Voltage Range
♦ -40°C to +95°C Operating Temperature Range
♦ 38-Pin TQFN (5mm x 7mm) Package
Burst-Mode Operation
Temperature Lookup Table (LUT)
Controlled by MON4 Voltage
Indexed LUT
Components, Up to 90V Bias Generation
Switching Frequency
Shutdown
Eight Monitors
Monitoring Functions, Four of Which are Either
Digital I/O or Analog Monitors
Maskable Laser Shutdown Capability
Calibration Data
Main Device Address
Address
Monitoring
2
C-Compatible Interface for Calibration and
Features
CC
,
1

Related parts for DS1875T+

DS1875T+ Summary of contents

Page 1

... BPON, GPON, or EPON Optical Triplexers SFF, SFP, and SFP+ Transceiver Modules APD Controller Ordering Information PART TEMP RANGE DS1875T+ -40°C to +95°C DS1875T+T&R -40°C to +95°C + Denotes a lead-free/RoHS-compliant package. T&R = Tape and reel Exposed pad. Pin Configuration TOP VIEW GND ...

Page 2

PON Triplexer and SFP Controller Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

TABLE OF CONTENTS (continued) Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

PON Triplexer and SFP Controller TABLE OF CONTENTS (continued) Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

ABSOLUTE MAXIMUM RATINGS Voltage Range on MON1–MON8, BEN, BMD, and TX-D Pins Relative to Ground .................................-0. Voltage Range SDA, SCL, CC D0–D3, and TX-F Pins Relative to Ground...............-0. Subject to not exceeding ...

Page 6

PON Triplexer and SFP Controller ELECTRICAL CHARACTERISTICS (DAC1 AND M4DAC +2.85V to +3.9V -40°C to +95°C, unless otherwise noted PARAMETER SYMBOL DAC Output Range DAC Output Resolution DAC Output Integral Nonlinearity DAC Output Differential ...

Page 7

PWM CHARACTERISTICS (V = +2.85V to +3.9V -40°C to +95°C, unless otherwise noted PARAMETER SYMBOL PWM-DAC Full-Scale Voltage V PWM-DAC PWM-DAC Resolution V Full-Scale Voltage PWM-DAC Error V Integral Nonlinearity PWM-DAC V Differential PWM-DAC Nonlinearity V ...

Page 8

PON Triplexer and SFP Controller ANALOG VOLTAGE MONITORING (V = +2.85V to +3.9V -40°C to +95°C, unless otherwise noted PARAMETER SYMBOL ADC Resolution Input/Supply Accuracy ACC (MON1–MON8 Update Rate for Temp, t FRAME:1 ...

Page 9

I C TIMING SPECIFICATIONS (V = +2.85V to +3.9V -40°C to +95°C, timing referenced PARAMETER SYMBOL SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus-Free Time Between STOP and START Condition START ...

Page 10

PON Triplexer and SFP Controller (V = +2.85V to +3.9V +25°C, unless otherwise noted SUPPLY CURRENT vs. SUPPLY VOLTAGE 9.0 SDA = SCL = V CC 8.5 8.0 7.5 +95°C 7.0 +25°C 6.5 6.0 5.5 -40°C ...

Page 11

T = +25°C, unless otherwise noted CALCULATED AND DESIRED % CHANGE IN V vs. MOD RANGING MOD 100 90 DESIRED 80 VALUE 70 CALCULATED 60 VALUE 000 ...

Page 12

PON Triplexer and SFP Controller (V = +2.85V to +3.9V +25°C, unless otherwise noted PWM DAC DNL 1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1. 128 160 192 224 DAC SETTING ...

Page 13

PIN NAME 1 BEN Burst-Enable Input. Triggers the samples for the APC and quick-trip monitors SDA I C Serial-Data Input/Output 2 3 SCL I C Serial-Clock Input 4 TX-F Transmit-Fault Output 5, 7, 11, 20, N.C. No Connection ...

Page 14

PON Triplexer and SFP Controller SDA INTERFACE SCL EEPROM 256 BYTES AT A0h SLAVE ADDRESS V CC MON1 MON2 MON3N MON3P MON4 MON[5:8] TEMP SENSOR SAMPLE BEN CONTROL BMD HBIAS QUICK-TRIP LIMIT HTXP ...

Page 15

PON Triplexer and SFP Controller IN+ IN- BEN+ BEN- DIS MOD SDA COMMUNICATION SCL TX-F FAULT OUTPUT DISABLE INPUT TX-D RECEIVER LOS LOSI OPEN-DRAIN LOS OUTPUT D0 D3 ADDITIONAL DIGITAL I/O MON[5:7] ADDITIONAL MONITORS COMP ______________________________________________________________________________________ 3.3V ...

Page 16

PON Triplexer and SFP Controller Detailed Description The DS1875 integrates the control and monitoring func- tionality required to implement a PON system using Maxim’s MAX3643 compact burst-mode laser driver. The compact laser-driver solution offers a considerable cost benefit by integrating ...

Page 17

When using autodetect mode or closed-loop mode, BEN should be equal long burst. In open-loop CC mode, BEN should be ground or any burst length. Modulation Control The MOD output is an 8-bit scaleable voltage output that ...

Page 18

PON Triplexer and SFP Controller BIAS and MOD Output as a Function of Transmit Disable (TX-D) If the TX-D pin is asserted (logic 1) during normal oper- ation, the outputs are disabled within t is deasserted (logic 0), the DS1875 ...

Page 19

A second bias-current moni- tor (BIAS MAX) compares the DS1875’s BIAS DAC’s code to a digital value stored in the ...

Page 20

PON Triplexer and SFP Controller TRIP CONDITION mCLK (525kHz) CAPTURE ALARM M3QT ALARM (UNLATCHED) Figure 4. M3QT Timing MON4 Figure 5. ADC Timing with EN5TO8B = 0 MON1 TEMP V MON2 MON3 CC t FRAME2 Figure 6. ADC Timing with ...

Page 21

Right-Shifting ADC Result If the weighting of the ADC digital reading must con- form to a predetermined full-scale value defined by a standard’s specification, then right-shifting can be used to adjust the predetermined full-scale analog measure- ment range while maintaining ...

Page 22

PON Triplexer and SFP Controller DETECTION OF FETG FAULT TX-D I BIAS V MOD FETG* *FETG DIR = 0 Figure 8. FETG/Output Disable Timing (Fault Condition Detected) Safety Shutdown (FETG) Output The FETG output has masking registers (separate from TX-F) ...

Page 23

Die Identification The DS1875 has an ID hard-coded to its die. Two regis- ters (Table 02h, Registers 86h–87h) are assigned for this feature. Byte 86h reads 75h to identify the part as the DS1875; byte 87h reads the die revision. ...

Page 24

PON Triplexer and SFP Controller MON3 TIMESLICE PERFORM FINE- MODE CONVERSION DID PRIOR MON3 Y TIMESLICE RESULT IN A COARSE CONVERSION? (LAST RSSI = 1 DID CURRENT FINE- Y MODE CONVERSION REACH MAX? N LAST RSSI = 0 ...

Page 25

Table 7. MON3 Hysteresis Threshold Values NO. OF RIGHT- FINE MODE SHIFTS (MAX) 0 FFF8h 1 7FFCh 2 3FFEh 3 1FFFh 4 0FFFh 5 07FFh 6 03FFh 7 01FFh * This is the minimum reported coarse-mode conversion. two thresholds. The ...

Page 26

PON Triplexer and SFP Controller than the PWM DAC level, the error amplifier increases the level on the COMP pin. The level on the COMP pin is compared to the signal from the oscillator and ramp generator to set the ...

Page 27

Stability and Compensation Component Selection The components connected to the COMP pin (R and C ) introduce a pole and zero that are neces- COMP sary for stable operation of the PWM controller (Figure 12). The dominant pole, POLE1, is ...

Page 28

PON Triplexer and SFP Controller COMP DS1875 APD OVERLOAD QUICK TRIP D2 MON3 Figure 12. PWM Controller Typical APD Bias Circuit SW DS1875 FB COMP Figure 13. PWM Controller Voltage Output Configuration 28 ______________________________________________________________________________________ ...

Page 29

SDA t BUF t LOW SCL t t HD:STA R STOP START NOTE: TIMING IS REFERENCED TO V AND V . IL(MAX) IH(MIN) 2 Figure 15 Timing Diagram Communication The following terminology is commonly used ...

Page 30

PON Triplexer and SFP Controller Byte Write: A byte write consists of 8 bits of infor- mation transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledge- ment from the slave to the master. The ...

Page 31

This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page one byte at a time wears ...

Page 32

PON Triplexer and SFP Controller SLAVE ADDRESS A0h (FIXED) DEC HEX 0 0h 00h AUXILIARY MEMORY EEPROM DEC HEX 128 80h 80h MON5–MON8 CONV 88h 89h TABLE 00h NO MEMORY FFh FFh 255 FFh 255 FFh Figure ...

Page 33

This register map shows each byte/word (2 bytes) in terms of the row the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent ...

Page 34

PON Triplexer and SFP Controller WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <2> 80 ADC VALUES MON5 VALUE 2 88–FF EMPTY EMPTY ACCESS <0> <1> <2> CODE Read All All Access See each bit/byte Write separately PW2 N/A Access ...

Page 35

WORD 0 ROW ROW (HEX) NAME BYTE 0/8 BYTE 1/9 <7> 80 PW1 EE EE <7> 88 PW1 EE EE <7> 90 PW1 EE EE <7> 98 PW1 EE EE <7> A0 PW1 EE EE <7> A8 PW1 EE EE ...

Page 36

PON Triplexer and SFP Controller WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <0> <8> 80 CONFIG MODE 0 SAMPLE <8> 88 CONFIG 1 RATE <8> 90 SCALE RESERVED 0 <8> 98 SCALE MON3 FINE SCALE 1 <8> A0 OFFSET ...

Page 37

WORD 0 ROW ROW (HEX) NAME BYTE 0/8 BYTE 1/9 <8> 80 PW2 EE EE <8> 88 PW2 EE EE <8> 90 PW2 EE EE <8> 98 PW2 EE EE <8> A0 PW2 EE EE <8> A8 PW2 EE EE ...

Page 38

PON Triplexer and SFP Controller WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <8> 80 LUT4 MOD <8> 88 LUT4 MOD <8> 90 LUT4 MOD <8> 98 LUT4 MOD <8> A0 LUT4 MOD <8> A8 LUT4 MOD <8> B0 LUT4 ...

Page 39

WORD 0 ROW ROW (HEX) NAME BYTE 0/8 BYTE 1/9 <8> 80 LUT6 M4DAC <8> 88 LUT6 M4DAC <8> 90 LUT6 M4DAC <8> 98 LUT6 M4DAC ACCESS <0> <1> <2> CODE Read All All Access See each bit/byte Write separately ...

Page 40

PON Triplexer and SFP Controller WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <8> 80 LUT8 BIAS_OL <8> 88 LUT8 BIAS_OL <8> 90 LUT8 BIAS_OL <8> 98 LUT8 BIAS_OL <8> A0 LUT8 BIAS_OL <8> A8 LUT8 BIAS_OL <8> B0 LUT8 ...

Page 41

WORD 0 ROW ROW (HEX) NAME BYTE 0/8 BYTE 1/9 <5> 00 AUX EE EE <5> 08 AUX EE EE <5> 10 AUX EE EE <5> 18 AUX EE EE <5> 20 AUX EE EE <5> 28 AUX EE EE ...

Page 42

PON Triplexer and SFP Controller Lower Memory, Register 00h to 01h: TEMP ALARM HI Lower Memory, Register 04h to 05h: TEMP WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 6 00h, 04h 01h, 05h ...

Page 43

Lower Memory, Register 08h to 09h: V Lower Memory, Register 0Ch to 0Dh: V Lower Memory, Register 10h to 11h: MON1 ALARM HI Lower Memory, Register 14h to 15h: MON1 WARN HI Lower Memory, Register 18h to 19h: MON2 ALARM ...

Page 44

PON Triplexer and SFP Controller Lower Memory, Register 0Ah to 0Bh: V Lower Memory, Register 0Eh to 0Fh: V Lower Memory, Register 12h to 13h: MON1 ALARM LO Lower Memory, Register 16h to 17h: MON1 WARN LO Lower Memory, Register ...

Page 45

Lower Memory, Register 30h to 5Fh: PW2 EE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 30h to 5Fh EE EE BIT 7 PW2 level access-controlled EEPROM. Lower Memory, Register 60h to 61h: TEMP VALUE FACTORY DEFAULT READ ACCESS WRITE ...

Page 46

PON Triplexer and SFP Controller Lower Memory, Register 62h to 63h: V Lower Memory, Register 64h to 65h: MON1 VALUE Lower Memory, Register 66h to 67h: MON2 VALUE Lower Memory, Register 68h to 69h: MON3 VALUE Lower Memory, Register 6Ah ...

Page 47

Lower Memory, Register 6Eh: STATUS POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE Write N/A All Access FETG SOFT 6Eh STATUS FETG BIT 7 FETG STATUS: Reflects the active state of FETG. The FETG DIR bit in Table 02h, Register ...

Page 48

PON Triplexer and SFP Controller Lower Memory, Register 6Fh: UPDATE POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS All + DS1875 Hardware MEMORY TYPE Volatile 6Fh TEMP RDY VCC RDY BIT 7 Update of completed conversions. At power-on, these bits ...

Page 49

Lower Memory, Register 70h: ALARM POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile 70h TEMP HI TEMP LO BIT 7 TEMP HI: High alarm status for temperature measurement. BIT (Default) Last measurement was ...

Page 50

PON Triplexer and SFP Controller Lower Memory, Register 71h: ALARM POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile 71h MON3 HI MON3 LO BIT 7 MON3 HI: High alarm status for MON3 measurement. BIT 7 0 ...

Page 51

Lower Memory, Register 72h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 72h RESERVED RESERVED BIT 7 BITS 7:4 RESERVED BIAS HI: High alarm status bias; fast comparison. BIT (Default) Last comparison was below threshold setting. ...

Page 52

PON Triplexer and SFP Controller Lower Memory, Register 74h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 74h TEMP HI TEMP LO BIT 7 TEMP HI: High warning status for temperature measurement. BIT (Default) Last measurement ...

Page 53

Lower Memory, Register 75h: WARN POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile 75h MON3 HI MON3 LO BIT 7 MON3 HI: High warning status for MON3 measurement. BIT (Default) Last measurement was ...

Page 54

PON Triplexer and SFP Controller Lower Memory, Register 78h: DOUT POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE M3QT SOFT 78h RESET M3QT BIT 7 M3QT RESET: Resets the latch for M3QT. The PWM does not begin normal operation until ...

Page 55

Lower Memory, Register 79h: DIN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 79h INV M3QT MUX M3QT BIT 7 INV M3QT: Status of inversion of M3QT (internal signal pin. MUX M3QT bit must be set to 1 ...

Page 56

PON Triplexer and SFP Controller Lower Memory, Register 7Bh to 7Eh: Password Entry (PWE) POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 7Bh 7Ch 7Dh 7Eh ...

Page 57

Table 00h, Register 80h to 81h: MON5 VALUE Table 00h, Register 82h to 83h: MON6 VALUE Table 00h, Register 84h to 85h: MON7 VALUE Table 00h, Register 86h to 87h: MON8 VALUE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE ...

Page 58

PON Triplexer and SFP Controller Table 01h, Register F8h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F8h TEMP HI TEMP LO BIT 7 Layout is identical to ALARM 1. VCC LO alarm is not set at power-on. 2. ...

Page 59

Table 01h, Register FAh: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FAh RESERVED RESERVED BIT 7 Layout is identical to ALARM 1. These bits are latched. They are cleared by power-down or a write with PW1 access. Table ...

Page 60

PON Triplexer and SFP Controller Table 01h, Register FDh: WARN 2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FDh MON3 HI MON3 LO BIT 7 Layout is identical to WARN 1. These bits are latched. They are cleared by ...

Page 61

Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h SEEB RESERVED BIT 7 SEEB (Default) Enables EEPROM writes to SEE bytes. BIT Disables EEPROM writes to SEE bytes during configuration, ...

Page 62

PON Triplexer and SFP Controller Table 02h, Register 81h: Temperature Index (TINDEX) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 81h 2 2 BIT 7 Holds the calculated index based on the temperature measurement. This index is used ...

Page 63

Table 02h, Register 83h: APC DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 83h 2 2 BIT 7 The digital value used for APC reference and recalled from Table 05h at the adjusted memory address found in ...

Page 64

PON Triplexer and SFP Controller Table 02h, Register 85h: M4DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 85h 2 2 BIT 7 The digital value used for M4DAC and recalled from Table 06h at the adjusted memory ...

Page 65

Table 02h, Register 88h: SAMPLE RATE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 88h SEE SEE BIT 7 BITS 7:6 SEE PWM_FR[1:0]: 2-bit frequency rate for the SW pulsed output used with PWM. When switching a lower to a ...

Page 66

PON Triplexer and SFP Controller Table 02h, Register 89h: CONFIG FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 89h FETG DIR TX-F LEN BIT 7 Configure the memory location and the polarity of the digital outputs. FETG DIR: Chooses the ...

Page 67

Table 02h, Register 8Ah: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. Table 02h, Register 8Bh: MOD RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Bh RESERVED RESERVED BIT 7 The lower nibble of ...

Page 68

PON Triplexer and SFP Controller Table 02h, Register 8Ch: DEVICE ADDRESS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 8Ch 2 2 BIT 7 This value becomes the I is set. If A0h is programmed to this register, ...

Page 69

Table 02h, Register 8Dh: COMP RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Dh RESERVED BIAS BIT 7 The upper nibble of this byte controls the full-scale range of the quick-trip monitoring for BIAS. The lower nibble of this ...

Page 70

PON Triplexer and SFP Controller Table 02h, Register 8Eh: RIGHT SHIFT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Eh RESERVED MON1 BIT 7 Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling ...

Page 71

Table 02h, Register 92h to 93h: V Table 02h, Register 94h to 95h: MON1 SCALE Table 02h, Register 96h to 97h: MON2 SCALE Table 02h, Register 98h to 99h: MON3 FINE SCALE Table 02h, Register 9Ah to 9Bh: MON4 SCALE ...

Page 72

PON Triplexer and SFP Controller Table 02h, Register A2h to A3h: V Table 02h, Register A4h to A5h: MON1 OFFSET Table 02h, Register A6h to A7h: MON2 OFFSET Table 02h, Register A8h to A9h: MON3 FINE OFFSET Table 02h, Register ...

Page 73

Table 02h, Register B0h to B3h: PW1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 B0h B1h B2h B3h 2 2 BIT 7 The PWE value ...

Page 74

PON Triplexer and SFP Controller Table 02h, Register B8h: FETG ENABLE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B8h TEMP EN VCC EN BIT 7 Configures the maskable interrupt for the FETG pin. TEMP EN: Enables/disables active interrupts on ...

Page 75

Table 02h, Register B9h: FETG ENABLE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B9h TXP HI EN TXP LO EN BIAS HI EN BIT 7 Configures the maskable interrupt for the FETG pin. TXP HI EN: Enables/disables active interrupts ...

Page 76

PON Triplexer and SFP Controller Table 02h, Register BAh: TX-F ENABLE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE BAh TEMP EN VCC EN BIT 7 Configures the maskable interrupt for the TX-F pin. TEMP EN: Enables/disables active interrupts on ...

Page 77

Table 02h, Register BBh: TX-F ENABLE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE BBh TXP HI EN TXP LO EN BIT 7 Configures the maskable interrupt for the TX-F pin. TXP HI EN: Enables/disables active interrupts on the TX-F ...

Page 78

PON Triplexer and SFP Controller Table 02h, Register BCh: HTXP FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 BCh 2 2 BIT 7 Fast comparison DAC threshold adjust for high TXP. This value is added to the APC ...

Page 79

Table 02h, Register BEh: HBIAS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 BEh 2 2 BIT 7 Fast-comparison DAC setting for high BIAS. Comparisons greater than V BIAS HI alarm. Table 02h, Register BFh: MAX BIAS FACTORY ...

Page 80

PON Triplexer and SFP Controller Table 02h, Register C0h: DPU FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C0h INV M3QT MUX M3QT BIT 7 INV M3QT: Inverts the internal M3QT signal to output pin D2 if MUX M3QT is ...

Page 81

Table 02h, Register C1h to C2h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Table 02h, Register C3h: M3QT DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 C3h 2 2 BIT 7 ...

Page 82

PON Triplexer and SFP Controller Table 02h, Register C5h to C6h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Table 02h, Register C7h: M4 LUT CNTL FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C7h ...

Page 83

Table 02h, Register C8h to C9h: MON5 SCALE Table 02h, Register CAh to CBh: MON6 SCALE Table 02h, Register CCh to CDh: MON7 SCALE Table 02h, Register CEh to CFh: MON8 SCALE FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE ...

Page 84

PON Triplexer and SFP Controller Table 02h, Register D8h to F7h: EMPTY Table 02h, Register F8h to F9h: MAN BIAS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE F8h RESERVED RESERVED 7 F9h 2 2 BIT 7 When BIAS EN ...

Page 85

Table 02h, Register FBh to FCh: BIAS DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE FBh BOL FCh 2 2 BIT 7 The bias open-loop bit (BOL) reflects the status of the BIAS current-control loop. If ...

Page 86

PON Triplexer and SFP Controller Table 02h, Register FEh: PWM DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 FEh 2 2 BIT 7 The digital value used for PWM integration of the FB pin recalled ...

Page 87

Table 03h, Register 80h to FFh: PW2 EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 80h to FFh EE EE BIT 7 PW2-protected EEPROM. Table 04h, Register 80h to C7h: MODULATION LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY ...

Page 88

PON Triplexer and SFP Controller Table 05h, Register 80h to A3h: APC TE LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80h to A3h 2 2 BIT 7 The APC TE LUT is a set of registers ...

Page 89

Table 06h, Register 80h to 9Fh: M4DAC LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80h to 9Fh 2 2 BIT 7 The M4DAC LUT is set of registers assigned to hold the voltage profile for the ...

Page 90

PON Triplexer and SFP Controller Table 07h, Register 80h to A3h: PWM REFERENCE LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80h to A3h 2 2 BIT 7 The PWM REFERENCE LUT is a set of registers ...

Page 91

Table 08h, Register 80h to C7h: BIAS OPEN-LOOP LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80h to C7h 2 2 BIT 7 The BIAS OPEN-LOOP LUT is a set of registers assigned to hold the temperature ...

Page 92

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 92 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products DESCRIPTION is a registered trademark of Maxim Integrated Products, Inc ...

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