DS1875T+ Maxim Integrated Products, DS1875T+ Datasheet - Page 22

• Manufacturer Part Number: DS1875T+
• Description: IC SFP CTRLR/TRIPLEXER 38-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS1875T+

• Applications: Fiber Optics
• Interface: I²C
• Voltage - Supply: 2.85 V ~ 3.9 V
• Package / Case: *
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PON Triplexer and SFP Controller
Figure 8. FETG/Output Disable Timing (Fault Condition Detected)
The FETG output has masking registers (separate from
TX-F) for the ADC alarms and the QT alarms to select
which comparisons cause it to assert. Unlike TX-F, the
FETG output is always latched. Its output polarity is
programmable to allow an external nMOS or pMOS to
open during alarms to shut off the laser-diode current.
If the FETG output triggers, indicating that the DS1875
is in shutdown, it requires TX-D, SOFT TX-D, or cycling
power to be reset. Under all conditions, when the ana-
log outputs are reinitialized after being disabled, all the
alarms with the exception of the V
are cleared. The V
prevent the output from attempting to operate when
inadequate V
adequate V
the outputs are enabled following the same sequence
as the power-up sequence.
As previously mentioned, the FETG is an output used to
disable the laser current through a series nMOS or
pMOS. This requires that the FETG output can sink or
source current. Because the DS1875 does not know if it
should sink or source current before V
V
impedance when V
Voltage Operation section for details and diagram). The
application circuit should use a pullup or pulldown
resistor on this pin that pulls FETG to the alarm/shut-
down state (high for a pMOS, low for a nMOS). Once
V
to the state determined by the FETG DIR bit (Table 02h,
22
POA
CC
______________________________________________________________________________________
is above V
, which triggers the EE recall, this output is high
CC
DETECTION OF
CC
FETG FAULT
Safety Shutdown (FETG) Output
POA
is present to clear the V
exists to operate the laser driver. Once
FETG*
*FETG DIR = 0
V
TX-D
I
MOD
BIAS
CC
, the DS1875 pulls the FETG output
CC
low alarm must remain active to
is below V
POA
CC
t
t
t
OFF
OFF
FETG:ON
low ADC alarm
(see the Low-
CC
CC
low alarm,
exceeds
Register 89h). Set FETG DIR to 0 if an nMOS is used
and 1 if a pMOS is used.
To determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1875’s alarm trap bytes
(ATB) through the I
F8h–FBh). The ATB has a bit for each alarm. Any time an
alarm occurs, regardless of the mask bit’s state, the
DS1875 sets the corresponding bit in the ATB. Active ATB
bits remain set until written to 0s through the I
On power-up, the ATB is 0s until alarms dictate otherwise.
FETG causes additional alarms that make it difficult to
determine the root cause of the problem. Therefore, no
updates are made to the ATB when FETG occurs.
Table 5. FETG, MOD, and BIAS Outputs
as a Function of TX-D and Alarm Sources
V
V
Yes
Yes
Yes
CC
Determining Alarm Causes Using the I
POA
t
FETG:OFF
>
t
t
ON
ON
TX-D
0
0
1
2
NONMASKED
C interface (Table 01h, Registers
FETG ALARM
X
0
1
FETG
FETG
FETG
FETG
DIR
DIR
DIR
2
Interface
C interface.
MOD AND
OUTPUTS
Disabled
Disabled
Enabled
BIAS
2
C