DS1875T+ Maxim Integrated Products, DS1875T+ Datasheet - Page 18

• Manufacturer Part Number: DS1875T+
• Description: IC SFP CTRLR/TRIPLEXER 38-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS1875T+

• Applications: Fiber Optics
• Interface: I²C
• Voltage - Supply: 2.85 V ~ 3.9 V
• Package / Case: *
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PON Triplexer and SFP Controller
If the TX-D pin is asserted (logic 1) during normal oper-
ation, the outputs are disabled within t
is deasserted (logic 0), the DS1875 turns on the MOD
output with the value associated with the present tem-
perature and initializes the BIAS using the same search
algorithm used at startup. When asserted, the SOFT
TX-D bit (Lower Memory, Register 6Eh) offers a soft-
ware control identical to the TX-D pin (see Figure 2).
Figure 2. TX-D Timing
As shown in Figure 3, the DS1875’s input comparator is
shared between the APC control loop and the three
quick-trip alarms (TXP HI, TXP LO, and BIAS HI). The
comparator polls the alarms in a multiplexed sequence.
Six of every eight comparator readings are used for
APC loop-bias current control. The other two updates
are used to check the HTXP/LTXP (monitor diode volt-
age) and the HBIAS (MON1) signals against the inter-
nal APC and BIAS reference. If the last APC
comparison was higher than the APC set point, it
makes an HTXP comparison, and if it is lower, it makes
an LTXP comparison. Depending on the results of the
comparison, the corresponding alarms and warnings
(TXP HI, TXP LO) are asserted or deasserted.
Figure 3. APC Loop and Quick-Trip Sample Timing
18
V
TX-D
I
MOD
BIAS
APC and Quick-Trip Shared Comparator
______________________________________________________________________________________
BIAS and MOD Output as a Function of
BEN
t
t
OFF
OFF
APC QUICK-TRIP
SAMPLE TIMES
t
t
ON
ON
Transmit Disable (TX-D)
t
FIRST
SAMPLE
t
APC
REP
OFF
SAMPLE
APC
. When TX-D
Timing
SAMPLE
APC
SAMPLE
APC
The DS1875 has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options suitable for
burst-mode transmitters. The rising edge of BEN trig-
gers the sample to occur, and the Update Rate register
(Table 02h, Register 88h) determines the sampling time.
The first sample occurs (t
BEN. The internal clock is asynchronous to BEN, caus-
ing a ±50ns uncertainty regarding when the first sample
will occur following BEN. After the first sample occurs,
subsequent samples occur on a regular interval, t
Table 2 shows the sample rate options available.
Updates to the TXP HI and TXP LO quick-trip alarms do
not occur during the BEN low time. The BIAS HI quick
trip can be sampled during the burst-low time. Any
Table 2. Update Rate Timing
* All codes greater than 1001b (1010b to 1111b) use the
maximum sample time of code 1001b.
APC_SR[3:0]
1001b*
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
SAMPLE
APC
SAMPLE
APC
FIRST SAMPLE
MINIMUM TIME
FROM BEN TO
(t FIRST ) ±50ns
HTXP/LTXP
SAMPLE
1350
1550
1750
2150
2950
3150
(ns)
350
550
750
950
FIRST
SAMPLE
) after the rising edge of
HBIAS
FOLLOWING FIRST
SAMPLE PERIOD
SAMPLE (t REP )
SAMPLE
APC
REPEATED
1200
1600
2000
2800
3200
3600
4400
6000
6400
(ns)
800
REP
.