DS1875T+ Maxim Integrated Products, DS1875T+ Datasheet - Page 9

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DS1875T+

Manufacturer Part Number
DS1875T+
Description
IC SFP CTRLR/TRIPLEXER 38-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1875T+

Applications
Fiber Optics
Interface
I²C
Voltage - Supply
2.85 V ~ 3.9 V
Package / Case
*
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
I
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: See the APC and Quick-Trip Shared Comparator Timing section for details.
Note 11: Guaranteed by design.
Note 12: I
Note 13: C
Note 14: EEPROM write begins after a STOP condition occurs.
2
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP
and START Condition
START Hold Time
START Setup Time
Data in Hold Time
Data in Setup Time
Capacitive Load for Each Bus Line
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
STOP Setup Time
EEPROM Write Time
CC
C TIMING SPECIFICATIONS
= +2.85V to +3.9V, T
PARAMETER
All voltages are referenced to ground. Current into IC is positive, and current out of the IC is negative.
Digital inputs are at rail. FETG is disconnected. SDA = SCL = V
See the Safety Shutdown (FETG) Output section for details.
Eight ranges allow the full scale to change from 625mV to 2.5V.
Eight ranges allow the full scale to change from 312.5mV to 1.25V.
This specification applies to the expected full-scale value for the selected range. See the COMP RANGING register
description for available full-scale ranges.
The output impedance of the DS1875 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56kΩ.
This specification applies to the expected full-scale value for the selected range. See the MOD RANGING register
description for available full-scale ranges.
The switching frequency is selectable between four values: 131.25kHz, 262.5kHz, 525kHz, and 1050kHz.
dard mode.
2
B
C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I
—Total capacitance of one bus line in pF.
_______________________________________________________________________________________
A
= -40°C to +95°C, timing referenced to V
SYMBOL
t
t
t
t
t
HD:STA
HD:DAT
SU:STO
SU:STA
SU:DAT
t
t
f
HIGH
t
LOW
PON Triplexer and SFP Controller
BUF
C
SCL
t
t
t
W
R
F
B
(Note 12)
(Note 13)
(Note 13)
(Note 14)
CONDITIONS
IL(MAX)
CC
. SW, DAC1, and M4DAC are not loaded.
and V
IH(MIN)
.) (See Figure 15.)
0.1C
0.1C
20 +
20 +
MIN
100
1.3
0.6
1.3
0.6
0.6
0.6
0
0
B
B
TYP
MAX
400
400
300
300
0.9
20
2
C stan-
UNITS
kHz
ms
μs
μs
μs
μs
μs
μs
ns
pF
ns
ns
μs
9

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