DS1875T+ Maxim Integrated Products, DS1875T+ Datasheet - Page 30

• Manufacturer Part Number: DS1875T+
• Description: IC SFP CTRLR/TRIPLEXER 38-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS1875T+

• Applications: Fiber Optics
• Interface: I²C
• Voltage - Supply: 2.85 V ~ 3.9 V
• Package / Case: *
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PON Triplexer and SFP Controller
30
Byte Write: A byte write consists of 8 bits of infor-
mation transferred from the master to the slave
(most significant bit first) plus a 1-bit acknowledge-
ment from the slave to the master. The 8 bits trans-
mitted by the master are done according to the bit
write definition and the acknowledgement is read
using the bit read definition.
Byte Read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit read definition, and the master
transmits an ACK using the bit write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
Slave Address Byte: Each slave on the I
responds to a slave addressing byte sent immedi-
ately following a START condition. The slave address
byte contains the slave address in the most signifi-
cant 7 bits and the R/W bit in the least significant bit.
The DS1875 responds to two slave addresses. The
auxiliary memory always responds to a fixed I
slave address, A0h. The Lower Memory and tables
00h–08h respond to I
be configured to any value between 00h–FEh using
the Device Address byte (Table 02h, Register 8Ch).
The user also must set the ASEL bit (Table 02h,
Register 89h) for this address to be active. By writ-
ing the correct slave address with R/W = 0, the mas-
ter indicates it will write data to the slave. If R/W = 1,
the master reads data from the slave. If an incorrect
slave address is written, the DS1875 assumes the
master is communicating with another I
and ignores the communications until the next
START condition is sent. If the main device’s slave
address is programmed to be A0h, access to the
auxiliary memory is disabled.
Memory Address: During an I
the DS1875, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
always the second byte transmitted during a write
operation following the slave address byte.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition. The
______________________________________________________________________________________
2
C slave addresses that can
2
C write operation to
I
2
C Protocol
2
C device
2
C bus
2
C
master must read the slave’s acknowledgement dur-
ing all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W = 0),
writes the memory address, writes up to 8 data
bytes, and generates a STOP condition. The DS1875
writes 1 to 8 bytes (one page or row) with a single
write transaction. This is internally controlled by an
address counter that allows data to be written to
consecutive addresses without transmitting a memo-
ry address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages result in the address
counter wrapping around to the beginning of the
present row.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that address-
es 06h and 07h contain 11h and 22h, respectively,
and the third data byte, 33h, is written to address
00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM
write time to elapse. Then the master can generate a
new START condition and write the slave address
byte (R/W = 0) and the first memory address of the
next memory row before continuing to write data.
Acknowledge Polling: Any time a EEPROM location
is written, the DS1875 requires the EEPROM write
time (t
tents of the page to EEPROM. During the EEPROM
write time, the device does not acknowledge its
slave address because it is busy. It is possible to
take advantage of that phenomenon by repeatedly
addressing the DS1875, which allows the next page
to be written as soon as the DS1875 is ready to
receive the data. The alternative to acknowledge
polling is to wait for a maximum period of t
elapse before attempting to write again to the
DS1875.
EEPROM Write Cycles: When EEPROM writes
occur to the memory, the DS1875 writes the whole
EEPROM memory page, even if only a single byte
on the page was modified. Writes that do not modify
all 8 bytes on the page are allowed and do not cor-
rupt the remaining bytes of memory on the same
page. Because the whole page is written, bytes that
W
) after the STOP condition to write the con-
W
to