DS1875T+ Maxim Integrated Products, DS1875T+ Datasheet - Page 31

• Manufacturer Part Number: DS1875T+
• Description: IC SFP CTRLR/TRIPLEXER 38-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS1875T+

• Applications: Fiber Optics
• Interface: I²C
• Voltage - Supply: 2.85 V ~ 3.9 V
• Package / Case: *
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DS1875 features 10 separate memory tables that
are internally organized into 8-byte rows.
The Lower Memory is addressed from 00h to 7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the table select byte.
Table 00h contains conversion results for MON5
through MON8.
Table 01h primarily contains user EEPROM (with PW1
level access) as well as some alarm and warning status
bytes.
were not modified during the transaction are still
subject to a write cycle. This can result in a whole
page being worn out over time by writing a single
byte repeatedly. Writing a page one byte at a time
wears the EEPROM out eight times faster than writ-
ing the entire page at once. The DS1875’s EEPROM
write cycles are specified in the Nonvolatile Memory
Characteristics table. The specification shown is at
the worst-case temperature. It can handle approxi-
mately 10 times that many writes at room tempera-
ture. Writing to SRAM-shadowed EEPROM memory
with SEEB = 1 does not count as a EEPROM write
cycle when evaluating the EEPROM’s estimated life-
time.
Reading a Single Byte from a Slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the
slave, the master generates a START condition,
writes the slave address byte with R/W = 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master
generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated
START condition, writes the slave address byte (R/W
= 1), reads data with ACK or NACK as applicable,
and generates a STOP condition.
______________________________________________________________________________________
Memory Organization
Memory Map
PON Triplexer and SFP Controller
Table 02h is a multifunction space that contains config-
uration registers, scaling and offset values, passwords,
interrupt registers, as well as other miscellaneous con-
trol bytes.
Table 03h is strictly user EEPROM that is protected by
a PW2-level password.
Table 04h contains a temperature-indexed LUT for
control of the modulation voltage. The modulation LUT
can be programmed in 2°C increments over the -40°C
to +102°C range. Access to this register is protected
by a PW2-level password.
Table 05h contains a temperature-indexed LUT that
allows the APC set point to change as a function of
temperature to compensate for Tracking Error (TE). The
APC LUT has 36 entries that determine the APC setting
in 4°C windows between -40°C to 100°C. Access to this
register is protected by a PW2-level password.
Table 06h contains a MON4-indexed LUT for control of
the M4DAC voltage. The MON4 LUT has 32 entries that
are configurable to act as one 32-entry LUT of two 16-
byte LUTs. When configured as one 32-byte LUT, each
entry corresponds to an increment of 1/32 the full scale.
When configured as two 16-byte LUTs, the first 16
bytes and the last 16 bytes each correspond to 1/16 full
scale. Either of the two sections is selected with a sep-
arate configuration bit. Access to this register is pro-
tected by a PW2-level password.
Table 07h contains a temperature-indexed LUT for
control of the PWM reference voltage (integration of FB
input). The PWM LUT has 36 entries that determine the
APC setting in 4°C windows between -40°C to +100°C.
Access to this register is protected by a PW2-level
password.
Table 08h contains a temperature-indexed LUT for
control of the BIAS current. The BIAS LUT can be pro-
grammed in 2°C increments over the 40°C to +102°C
range. Access to this register is protected by a PW2-
level password.
Auxiliary Memory (Device A0h) contains 256 bytes of
EE memory accessible from address 00h–FFh. It is
selected with the device address of A0h.
See the Register Descriptions section for a more com-
plete detail of each byte’s function, as well as for
read/write permissions for each byte.
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