MCP3909EV-MCU16 Microchip Technology, MCP3909EV-MCU16 Datasheet - Page 21

EVALUATION BOARD FOR MCP3909

MCP3909EV-MCU16

Manufacturer Part Number
MCP3909EV-MCU16
Description
EVALUATION BOARD FOR MCP3909
Manufacturer
Microchip Technology
Datasheets

Specifications of MCP3909EV-MCU16

Number Of Adc's
2
Number Of Bits
16
Sampling Rate (per Second)
15k
Data Interface
Serial
Inputs Per Adc
1 Differential
Input Range
±1 V
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
MCP3909
Silicon Manufacturer
Microchip
Application Sub Type
ADC
Kit Application Type
Data Converter
Silicon Core Number
MCP3909
Kit Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Hardware Description
2.3.1
Samples And Processing
Input capture IC
on the dsPIC33F is used to detect if A/D conversion is complete.
1
However, not all MCP3909 device samples are stored in the MCU, depending on the
parameter being calculated. The ADC conversion rate of the MCP3909 device is
determined by the frequency of the master clock (3.378 MHz for the case of a 50 Hz
line), and the output data rate is MCLK/256 or 12.8 ksps. After each conversion is
complete, a Data Ready signal is generated by the SDO of the MCP3909 device. The
signal is fed into IC
, allowing the Interrupt Service Routine (ISR) of IC
to read the
1
1
data. When the MCP3909 device outputs data, it first sends an ADC result of the
voltage channel, then an ADC result of the current channel, with MSB first.
As noted, not all MCP3909 device samples are used for calculating all the parameters.
In practice, 6.4 ksps sampling rate is required, which means only 1 output data is used
for every 2 data sampled. For 50 Hz input signal, 6.4 ksps sampling rate will take 128
samples for each cycle. For example, the active power metering is computed based on
this condition.
But for other parameters for which precision is not critical, such as reactive energy,
voltage, current and frequency, the sampling rate may be reduced to save data storage
space and processing time. In this design, the 3.2 ksps sampling rate is used, which
means only 1 result is stored for every 4 ADC conversions.
After each conversion, a positive pulse with the width of 4 clock cycles is output by the
SDO pin of the MCP3909 device. IC
is used to detect the falling edge of the pulse and
1
generate an interrupt for every 2 falling edges, i.e., 1 data is read for every 2 conver-
sions, thus realizing 6.4 ksps sampling rate.
© 2009 Microchip Technology Inc.
DS51723A-page 21

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