ADZS-BF527-EZLITE Analog Devices Inc, ADZS-BF527-EZLITE Datasheet - Page 11
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ADZS-BF527-EZLITE
Manufacturer Part Number
ADZS-BF527-EZLITE
Description
BOARD EVAL ADSP-BF527
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
DSPr
Datasheet
1.ADZS-BF527-EZLITE.pdf
(80 pages)
Specifications of ADZS-BF527-EZLITE
Featured Product
Blackfin® BF50x Series Processors
Contents
Evaluation Board
Silicon Manufacturer
Analog Devices
Core Architecture
Blackfin
Features
USB-based, PC-hosted Tool Set
Silicon Core Number
ADSP-BF527
Silicon Family Name
Blackfin
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADSP-BF527
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Preliminary Technical Data
SERIAL PORTS
The processors incorporate two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiproces-
sor communications. The SPORTs support the following
features:
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The processors have an SPI-compatible port that enables the
processor to communicate with multiple SPI-compatible
devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI
chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL7–1) let
the processor select other SPI devices. The SPI select pins are
reconfigured general-purpose I/O pins. Using these pins, the
• I
• Bidirectional operation – Each SPORT has two sets of inde-
• Buffered (8-deep) transmit and receive ports – Each port
• Clocking – Each transmit and receive port can either use an
• Word length – Each SPORT supports serial data words
• Framing – Each transmit and receive port can run with or
• Companding in hardware – Each SPORT can perform
• DMA operations with single-cycle overhead – Each SPORT
• Interrupts – Each transmit and receive port generates an
• Multichannel capability – Each SPORT supports 128 chan-
pendent transmit and receive pins, enabling eight channels
of I
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
external serial clock or generate its own, in frequencies
ranging from (f
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without
additional latencies.
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer, or buffers,
through DMA.
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
2
S capable operation.
2
S stereo audio.
SCLK
/131,070) Hz to (f
SCLK
/2) Hz.
Rev. PrG | Page 11 of 80 | February 2009
SPI port provides a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA channel,
configurable to support transmit or receive data streams. The
SPI’s DMA channel can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
Where the 16-bit SPI_BAUD register contains a value of 2
to 65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTS
The processors provide two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
one or two stop bits, and none, even, or odd parity. Each UART
port supports two modes of operation:
Each UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
The UART port’s clock rate is calculated as:
Where the 16-bit UART_Divisor comes from the UART_DLH
(most significant 8 bits) and UART_DLL (least significant
8 bits) registers.
• PIO (programmed I/O) – The processor sends or receives
• DMA (direct memory access) – The DMA controller trans-
• Supporting bit rates ranging from (f
• Supporting data formats from seven to 12 bits per frame.
• Both transmit and receive operations can be configured to
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
(f
generate maskable interrupts to the processor.
SCLK
ADSP-BF522/523/524/525/526/527
/16) bits per second.
UART Clock Rate
SPI Clock Rate
=
=
---------------------------------------------- -
16 UART_Divisor
----------------------------------- -
2
SPI_BAUD
f
SCLK
f
SCLK
SCLK
/1,048,576) to