ADZS-BF527-EZLITE Analog Devices Inc, ADZS-BF527-EZLITE Datasheet - Page 24

• Manufacturer Part Number: ADZS-BF527-EZLITE
• Description: BOARD EVAL ADSP-BF527
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADZS-BF527-EZLITE

• Featured Product: Blackfin® BF50x Series Processors
• Contents: Evaluation Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: Blackfin
• Features: USB-based, PC-hosted Tool Set
• Silicon Core Number: ADSP-BF527
• Silicon Family Name: Blackfin
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF522/523/524/525/526/527
Table 10. Signal Descriptions (Continued)
Signal Name
Port H: GPIO and Multiplexed Peripherals
PG0/HWAIT
PG1/SPISS/SPISEL1
PG2/SCK
PG3/MISO/DR0SECA
PG4/MOSI/DT0SECA
PG5/TMR1/PPI_FS2
PG6/DT0PRIA/TMR2/PPI_FS3
PG7/TMR3/DR0PRIA/UART0TX
PG8/TMR4/RFS0A/UART0RX/TACI4
PG9/TMR5/RSCLK0A/TACI5
PG10/TMR6/TSCLK0A/TACI6
PG11/TMR7/HOST_WR
PG12/DMAR1/UART1TXA/HOST_ACK
PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2
PG14/TSCLK0A1/MDC/HOST_RD
PG15
PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0
PH1/ND_D1/ERxER/HOST_D1
PH2/ND_D2/MDIO/HOST_D2
PH3/ND_D3/ETxEN/HOST_D3
PH4/ND_D4/MIITxCLK/RMIIREF_CLK/HOST_D4 I/O
PH5/ND_D5/ETxD0/HOST_D5
PH6/ND_D6/ERxD0/HOST_D6
PH7/ND_D7/ETxD1/HOST_D7
PH8/SPISEL4/ERxD1/HOST_D8/TACLK2
PH9/SPISEL5/ETxD2/HOST_D9/TACLK3
PH10/ND_CE/ERxD2/HOST_D10
PH11/ND_WE/ETxD3/HOST_D11
PH12/ND_RE/ERxD3/HOST_D12
PH13/ND_BUSY/ERxCLK/HOST_D13
PH14/ND_CLE/ERxDV/HOST_D14
PH15/ND_ALE/COL/HOST_D15
3
/TFS0A/MII PHYINT/RMII MDINT/HOST_CE I/O
Type Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Rev. PrG | Page 24 of 80 | February 2009
Capture Input 2
GPIO/Boot Host Wait
GPIO/SPI Slave Select Input/SPI Slave Select 1
GPIO/SPI Clock
GPIO/SPI Master In Slave Out/Sport 0 Alternate Receive Data Secondary
GPIO/SPI Master Out Slave In/Sport 0 Alternate Transmit Data Secondary
GPIO/Timer1/PPI Frame Sync2
GPIO/SPORT0 Alternate Primary Transmit Data / Timer2 / PPI Frame Sync3
GPIO/Timer3/Sport 0 Alternate Receive Data Primary/UART0 Transmit
GPIO/Timer 4/Sport 0 Alternate Receive Clock/Frame Sync
/UART0 Receive/Alternate Capture Input 4
GPIO/Timer5/Sport 0 Alternate Receive Clock
/Alternate Capture Input 5
GPIO/Timer 6 /Sport 0 Alternate Transmit
/Alternate Capture Input 6
GPIO/Timer7/Host DMA Write Enable
GPIO/DMA Request 1/Alternate UART1 Transmit/Host DMA Acknowledge
GPIO/DMA Request 0/Alternate UART1 Receive/Host DMA Address/Alternate
GPIO/SPORT0 Alternate 1 Transmit/Ethernet Management Channel Clock
/Host DMA Read Enable
GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII PHY Interrupt/RMII
Management Channel Data Interrupt/Host DMA Chip Enable
GPIO/NAND D0/Ethernet MII or RMII Carrier Sense/Host DMA D0
GPIO/NAND D1/Ethernet MII or RMII Receive Error/Host DMA D1
GPIO/NAND D2/Ethernet Management Channel Serial Data/Host DMA D2
GPIO/NAND D3/Ethernet MII Transmit Enable/Host DMA D3
GPIO/NAND D4/Ethernet MII or RMII Reference Clock/Host D4
GPIO/NAND D5/Ethernet MII or RMII Transmit D0/Host DMA D5
GPIO/NAND D6/Ethernet MII or RMII Receive D0/Host DMA D6
GPIO/NAND D7/Ethernet MII or RMII Transmit D1/Host DMA D7
GPIO/Alternate Capture Input 2/Ethernet MII or RMII Receive D1/Host DMA D8
/SPI Slave Select 4
GPIO/SPI Slave Select 5/Ethernet MII Transmit D2/Host DMA D9
/Alternate Timer Clock 3
GPIO/NAND Chip Enable/Ethernet MII Receive D2/Host DMA D10
GPIO/NAND Write Enable/Ethernet MII Transmit D3/Host DMA D11
GPIO/NAND Read Enable/Ethernet MII Receive D3/Host DMA D12
GPIO/NAND Busy/Ethernet MII Receive Clock/Host DMA D13
GPIO/NAND Command Latch Enable/Ethernet MII or RMII Receive Data
Valid/Host DMA D14
GPIO/NAND Address Latch Enable/Ethernet MII Collision/Host DMA Data 15
2
Preliminary Technical Data
Driver
Type
C
C
D
C
C
C
C
C
C
D
D
C
C
C
D
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1