ADZS-BF527-EZLITE Analog Devices Inc, ADZS-BF527-EZLITE Datasheet - Page 50

• Manufacturer Part Number: ADZS-BF527-EZLITE
• Description: BOARD EVAL ADSP-BF527
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADZS-BF527-EZLITE

• Featured Product: Blackfin® BF50x Series Processors
• Contents: Evaluation Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: Blackfin
• Features: USB-based, PC-hosted Tool Set
• Silicon Core Number: ADSP-BF527
• Silicon Family Name: Blackfin
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF522/523/524/525/526/527
Table 39. Serial Ports—Enable and Three-State
1
Parameter
Switching Characteristics
t
t
t
t
Referenced to drive edge.
DTENE
DDTTE
DTENI
DDTTI
RSCLKx
DRx
RFSx
TSCLKx
DTx
TFSx
DATA RECEIVE—INTERNAL CLOCK
DATA TRANSMIT—INTERNAL CLOCK
t
HOFSI
t
HOFSI
t
HDTI
DRIVE
DRIVE
EDGE
EDGE
Data Enable Delay from External TSCLKx
Data Disable Delay from External TSCLKx
Data Enable Delay from Internal TSCLKx
Data Disable Delay from Internal TSCLKx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DFSI
t
t
DFSI
DDTI
TSCLKx
t
t
SCLKIW
SCLKIW
DTx
t
t
SFSI
t
SDRI
SFSI
DRIVE
SAMPLE
SAMPLE
EDGE
EDGE
Figure 24. Serial Ports — Enable and Three-State
Rev. PrG | Page 50 of 80 | February 2009
t
DTENE/I
t
t
HDRI
t
HFSI
HFSI
1
1
Figure 23. Serial Ports
1
1
t
DDTTE/I
Min
–2.0
0.0
DRIVE
V
ADSP-BF522/524/526
1.8 V
DDEXT
RSCLKx
RFSx
DRx
TSCLKx
DTx
TFSx
Max
10.0
=
3.0
DATA RECEIVE—EXTERNAL CLOCK
DATA TRANSMIT—EXTERNAL CLOCK
t
t
HOFSE
HOFSE
t
HDTE
Min
–2.0
0.0
DRIVE
DRIVE
2.5/3.3 V
EDGE
EDGE
V
DDEXT
t
t
Max
10.0
DFSE
DFSE
3.0
=
Preliminary Technical Data
t
DDTE
t
t
SCLKEW
SCLKEW
Min
–2.0
0.0
V
ADSP-BF523/525/527
1.8 V
DDEXT
t
t
t
SFSE
SDRE
SFSE
t
t
SCLK
SCLK
Max
=
+1
+1
SAMPLE
SAMPLE
EDGE
EDGE
Min
–2.0
0.0
2.5/3.3 V
V
DDEXT
t
t
SCLK
SCLK
Max Unit
=
t
t
t
HDRE
HFSE
HFSE
+1 ns
+1 ns
ns
ns