C8051F326DK Silicon Laboratories Inc, C8051F326DK Datasheet - Page 127
![KIT DEV FOR C8051F326/7](/photos/9/23/92331/c8051f326dk_sml.jpg)
C8051F326DK
Manufacturer Part Number
C8051F326DK
Description
KIT DEV FOR C8051F326/7
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F326DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F326/F327
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F326
Silicon Family Name
C8051F32x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F326, C8051F327
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1306
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14. Timers
Each MCU includes two 16-bit timers compatible with those found in the standard 8051. These timers can
be used to measure time intervals and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly
identical and have four primary modes of operation.
Timers 0 and 1 may be clocked by one of four sources, determined by the Timer Mode Select bits (T1M-
T0M) and the Clock Scale bits (SCA1-SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See Figure 14.3 for pre-scaled clock selection). Timer 0/1 may
then be configured to use this pre-scaled clock signal or the system clock.
Timers 0 and 1 have a gate mode which allows the timer to run only when an external interrupt is active
(/INT0 for Timer 0 and /INT1 for Timer 1. This mode facilitates pulse width measurements on input on P0.2
(Timer 0) and Low Frequency oscillator calibration when used with Timer 1.
14.1. Timer 0 and Timer 1 Operating Modes
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as
well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register (Section
“6.3.5. Interrupt Register Descriptions” on page 50); Timer 1 interrupts can be enabled by setting the ET1
bit in the IE register (SFR Definition 6.7). Both timers operate in one of four primary modes selected by set-
ting the Mode Select bits T1M1-T0M0 in the Timer Mode register (TMOD). Each timer can be configured
independently. Each operating mode is described below.
13-bit timer
16-bit timer
8-bit timer with auto-reload
Two 8-bit timers (Timer 0 only)
Table 14.1. Timer Modes
Timer 0 and Timer 1 Modes:
Rev. 1.1
C8051F326/7
127
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