C8051F326DK Silicon Laboratories Inc, C8051F326DK Datasheet - Page 46

• Manufacturer Part Number: C8051F326DK
• Description: KIT DEV FOR C8051F326/7
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F326DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F326/F327
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F326
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F326, C8051F327
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1306

C8051F326/7
46
Bit7:
Bit6:
Bit5:
Bits4–3: RS1-RS0: Register Bank Select.
Bit2:
Bit1:
Bit0:
Bits7–0: ACC: Accumulator.
ACC.7
R/W
R/W
CY
Bit7
Bit7
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic opera-
tions.
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
These bits select which register bank is used during register accesses.
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This register is the accumulator for arithmetic operations.
RS1
ACC.6
0
0
1
1
R/W
R/W
AC
Bit6
Bit6
SFR Definition 6.4. PSW: Program Status Word
RS0
0
1
0
1
ACC.5
R/W
SFR Definition 6.5. ACC: Accumulator
R/W
Bit5
Bit5
F0
Register Bank
ACC.4
RS1
R/W
R/W
Bit4
Bit4
0
1
2
3
Rev. 1.1
ACC.3
RS0
R/W
R/W
Bit3
Bit3
0x00–0x07
0x08–0x0F
0x10–0x17
0x18–0x1F
Address
ACC.2
R/W
R/W
OV
Bit2
Bit2
ACC.1
R/W
R/W
Bit1
Bit1
F1
(bit addressable)
(bit addressable)
PARITY
ACC.0
R/W
Bit0
Bit0
R
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
0xD0
0xE0