C8051F326DK Silicon Laboratories Inc, C8051F326DK Datasheet - Page 95

• Manufacturer Part Number: C8051F326DK
• Description: KIT DEV FOR C8051F326/7
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F326DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F326/F327
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F326
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F326, C8051F327
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1306

12.5. FIFO Management
256 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoint0
and Endpoint1 as shown in Figure 12.3. FIFO space allocated for Endpoint1 is split into an IN and an OUT
endpoint.
12.5.1. FIFO Split Mode
The FIFO space for Endpoint1 is split such that the upper 64 bytes of the FIFO space is used by the IN
endpoint, and the lower 128 bytes is used by the OUT endpoint.
The FIFO space for Endpoint0 is not split. The 64 byte FIFO space forms a single IN or OUT FIFO.
Endpoint0 can transfer data in one direction at a time. The endpoint direction (IN/OUT) is determined by
the DIRSEL bit in the corresponding endpoint’s EINCSRH register (see Figure 12.20).
12.5.2. FIFO Double Buffering
The Endpoint1 FIFO can be configured for double-buffered mode. In this mode, the maximum packet size
is halved and the FIFO may contain two packets at a time. This mode is only available for Endpoint1. Dou-
ble buffering may be enabled for the IN Endpoint and/or the OUT endpoint. See Table 12.3 for a list of
maximum packet sizes for each FIFO configuration.
Endpoint
Number
0x03FF
0x0000
0
1
0xC0
0xBF
0xFF
0x00
Split Mode
Enabled?
OUT (128 bytes)
N/A
IN (64 bytes)
(1024 bytes)
Y
User XRAM
Endpoint0
Endpoint1
(64 bytes)
Figure 12.3. USB FIFO Allocation
Table 12.3. FIFO Configurations
(Double Buffer Disabled /
Maximum IN Packet Size
Enabled)
Rev. 1.1
64 / 32
USB Clock Domain
System Clock Domain
Endpoint1 (Split IN/OUT)
64
Endpoint0 (IN/OUT)
Size (Double Buffer Dis-
Maximum OUT Packet
Control Endpoint
abled / Enabled)
128 / 64
C8051F326/7
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