C8051F326DK Silicon Laboratories Inc, C8051F326DK Datasheet - Page 71
C8051F326DK
Manufacturer Part Number
C8051F326DK
Description
KIT DEV FOR C8051F326/7
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F326DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F326/F327
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F326
Silicon Family Name
C8051F32x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F326, C8051F327
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1306
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10. Oscillators
C8051F326/7 devices include a programmable internal oscillator, an external clock input circuit, a low fre-
quency internal oscillator, and a 4x Clock Multiplier. The internal oscillator can be enabled/disabled and
calibrated using the OSCICN and OSCICL registers, as shown in Figure 10.1. The Low Frequency oscilla-
tor can be enabled/disabled and calibrated using the OSCLCN register, as shown in Figure 10.3. The sys-
tem clock (SYSCLK) can be derived from the internal oscillator, external clock, low frequency oscillator, or
the 4x Clock Multiplier divided by 2. The USB clock (USBCLK) can be derived from the internal oscillator
divided by 2, external clock, or 4x Clock Multiplier. Oscillator electrical specifications are given in
Table 10.3 on page 78.
10.1. Programmable Internal Oscillator
All C8051F326/7 devices include a programmable internal oscillator that defaults as the system clock after
a system reset. The internal oscillator period can be adjusted via the OSCICL register. On C8051F326/7
devices, OSCICL is factory calibrated to obtain a 12 MHz frequency. Electrical specifications for the preci-
sion internal oscillator are given in Table 10.3 on page 78. Note that the system clock may be derived from
the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN.
The divide value defaults to 8 following a reset.
CMOS
Clock
XTAL2
OSCICL
Low Frequency
OSCLF
Figure 10.1. Oscillator Diagram
Programmable
Internal Clock
Generator
Oscillator
Circuit
Input
EN
EN
IOSC
EXOSC
OSCICN
EXOSC
Rev. 1.1
IOSC
CLKMUL
n
Clock Multiplier
OSCLCN
x 2
x 2
OFF (0 Hz)
IOSC / 2
EXOSC
C8051F326/7
CLKSEL
SYSCLK
USBCLK
71
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