C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 131
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C8051T630DK
Manufacturer Part Number
C8051T630DK
Description
KIT DEV FOR C8051T630 FAMILY
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T630DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T63x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T630, T631, T632, T633, T634 and T635 MCUs
For Use With
336-1465 - BOARD SOCKET DAUGHTER 20-QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1464
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The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 21.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “24. Timers” on page 169.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 21.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 21.2.
Figure 21.4 shows the typical SCL generation described by Equation 21.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 21.1.
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
Timer Source
Overflows
SCL
LOW
Equation 21.1. Minimum SCL High and Low Times
. The actual SCL output may vary due to other devices on the bus (SCL may be
T
Low
Figure 21.4. Typical SMBus SCL Generation
Table 21.1. SMBus Clock Source Selection
SMBCS1
T
Equation 21.2. Typical SMBus Bit Rate
HighMin
0
0
1
1
BitRate
SMBCS0
=
T
High
T
0
1
0
1
LowMin
=
f
--------------------------------------------- -
ClockSourceOverflow
Rev. 1.0
Timer 2 High Byte Overflow
=
Timer 2 Low Byte Overflow
SMBus Clock Source
--------------------------------------------- -
f
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
3
C8051T630/1/2/3/4/5
1
SCL High Timeout
HIGH
is typically
131
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