C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 136
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C8051T630DK
Manufacturer Part Number
C8051T630DK
Description
KIT DEV FOR C8051T630 FAMILY
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T630DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T63x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T630, T631, T632, T633, T634 and T635 MCUs
For Use With
336-1465 - BOARD SOCKET DAUGHTER 20-QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1464
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C8051T630/1/2/3/4/5
21.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 21.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 21.3) and the SMBus Slave Address Mask register (SFR Definition 21.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
136
ARBLOST
MASTER
TXMODE
ACKRQ
STO
ACK
STA
Bit
SI
Table 21.3. Sources for Hardware Changes to SMB0CN
A START is generated.
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low
(ACKNOWLEDGE).
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Set by Hardware When:
Rev. 1.0
A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
Must be cleared by software.
A pending STOP is generated.
After each ACK cycle.
Each time SI is cleared.
The incoming ACK value is high
(NOT ACKNOWLEDGE).
Must be cleared by software.
Cleared by Hardware When:
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