MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 19
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 19 of 117
- Download datasheet (2Mb)
Table 16
Table 17
Figure 3
Freescale Semiconductor
At recommended operating conditions.
At recommended operating conditions.
AC input low voltage
AC input high voltage
Controller skew for MDQS—MDQ/MECC/MDM
Notes:
1. t
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
3. Maximum DDR1 frequency is 400 MHz.
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
determined by the following equation: t
absolute value of t
CISKEW
shows the DDR SDRAM input timing diagram.
provides the input AC timing specifications for the DDR SDRAM when GV
provides the input AC timing specifications for the DDR SDRAM interface.
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
MDQS[n]
MDQ[x]
MCK[n]
MCK[n]
Parameter
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 16. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
CISKEW
Parameter
. See
Table 17. DDR SDRAM Input AC Timing Specifications
Figure 3. DDR SDRAM Input Timing Diagram (t
Figure
3.
t
DISKEW
MCK
t
DISKEW
533 MHz
400 MHz
333 MHz
= ± (T/4 – abs(t
Symbol
V
V
IH
IL
D0
Symbol
t
CISKEW
CISKEW
MV
D1
t
DISKEW
REF
)), where T is the clock period and abs(t
Min
—
+ 0.31
–300
–365
–390
Min
DISKEW
MV
REF
Max
—
Max
)
300
365
390
– 0.31
DISKEW
DD
DDR and DDR2 SDRAM
. This can be
(typ) = 2.5 V.
Unit
Unit
ps
V
V
CISKEW
Notes
Notes
) is the
1, 2
—
—
—
—
3
19
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