MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 72
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MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High-Speed Serial Interfaces (HSSI)
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
16.2.4.1
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to –0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread
spectrum clock source.
16.3
Figure 55
The DC and AC specification of SerDes data lanes are defined in the section below (PCI Express or
SGMII) in this document based on the application usage:
Please note that external AC Coupling capacitor is required for the above serial transmission protocols
with the capacitor value defined in specification of each protocol section.
72
•
•
•
•
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
V
Section 8.3.1, “The DBWO Signal”
Section 17.2, “AC Requirements for PCI Express SerDes Clocks”
Section 8.3, “SGMII Interface Electrical Characteristics”
Section 17, “PCI Express”
CROSS MEDIAN
SerDes Transmitter and Receiver Reference Circuits
shows the reference circuits for SerDes data lane’s transmitter and receiver.
Spread Spectrum Clock
Figure 54. Single-Ended Measurement Points for Rise and Fall Time Matching
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Transmitter
Figure 55. SerDes Transmitter and Receiver Reference Circuits
50 Ω
50 Ω
SD1_TXn or
SD2_TXn
SD1_TXn or
SD2_TXn
V
V
CROSS MEDIAN
CROSS MEDIAN
SD1_RXn or
SD2_RXn
SD1_RXn or
SD2_RXn
SDn_REF_CLK
SDn_REF_CLK
V
CROSS MEDIAN
+ 100 mV
– 100 mV
50 Ω
50 Ω
Receiver
T
FALL
Freescale Semiconductor
T
RISE