MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 35

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 17
Figure 18
8.7
This section describes the TBI transmit and receive AC timing specifications.
Freescale Semiconductor
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%.
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t
with the appropriate letter: R (rise) or F (fall).
TBI AC Timing Specifications
provides the AC test load for eTSEC.
shows the MII receive AC timing diagram.
Parameter/Condition
(first two letters of functional block)(reference)(state)(signal)(state)
RXD[3:0]
RX_CLK
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
RX_DV
RX_ER
Table 33. MII Receive AC Timing Specifications (continued)
Output
MRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
Figure 18. MII Receive AC Timing Diagram
t
t
MRXH
MRDVKH
MRX
Figure 17. eTSEC AC Test Load
t
MRX
clock reference (K) going to the low (L) state or hold time. Note that, in general,
Z
MRDXKL
0
= 50 Ω
Symbol
t
t
MRDXKH
MRDVKH
t
t
Valid Data
MRXR
MRXF
symbolizes MII receive timing (GR) with respect to the time data input
1
t
MRXF
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Enhanced Three-Speed Ethernet (eTSEC), MII Management
10.0
10.0
Min
1.0
1.0
R
t
L
MRDXKL
t
MRXR
= 50 Ω
Typ
—
—
—
—
LV
DD
MRDVKH
/2
Max
4.0
4.0
—
—
MRX
symbolizes MII receive
clock reference (K)
Unit
ns
ns
ns
ns
Notes
—
—
—
—
for
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