MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 31
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 31 of 117
- Download datasheet (2Mb)
Timing diagrams for FIFO appear in
Freescale Semiconductor
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
(continued)At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Fall time TX_CLK (80%–20%)
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN
hold time
Note:
1. Data valid t
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RX_CLK to RXD[7:0], RX_DV, RX_ER hold time
(Min setup = Cycle time – Max hold).
GTX_CLK
RXD[7:0]
RX_CLK
TXD[7:0]
FITDV
RX_ER
RX_DV
Parameter/Condition
Parameter/Condition
TX_EN
TX_ER
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
to GTX_CLK Min setup time is a function of clock period and max hold time.
Table 28. FIFO Mode Transmit AC Timing Specification (continued)
Table 29. FIFO Mode Receive AC Timing Specification
t
t
FIRH
FITH
Figure 11. FIFO Transmit AC Timing Diagram
Figure 12. FIFO Receive AC Timing Diagram
t
t
t
FIR
FIRDV
FIT
t
FITDV
Figure 11
t
FIRH
Valid Data
Symbol
Symbol
t
t
t
and
t
FIRDX
FITDX
t
FIRDV
t
t
FIRR
t
FIRF
FITF
FIRJ
FIR
/t
FIRH
Figure
Enhanced Three-Speed Ethernet (eTSEC), MII Management
t
12.
FITDX
Min
Min
0.5
1.5
0.5
45
—
—
—
—
—
t
FIRDX
Typ
Typ
8.0
50
—
—
—
—
—
—
—
t
t
FITF
FIRF
Max
0.75
Max
0.75
0.75
250
3.0
55
—
—
—
t
FITR
t
FIRR
Unit
Unit
ns
ns
ns
ps
ns
ns
ns
ns
%
Notes
Notes
—
—
—
—
—
—
—
—
1
31
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