CY3220LINBUS-RD Cypress Semiconductor Corp, CY3220LINBUS-RD Datasheet - Page 15

• Manufacturer Part Number: CY3220LINBUS-RD
• Description: KIT REF DESIGN LIN BUS
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®r

Specifications of CY3220LINBUS-RD

• Main Purpose: Interface, LIN
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CY8C27143, CY8C27443
• Processor To Be Evaluated: CY8C27143-24PXI and CY8C27443-24PXI
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1926

LIN Bus 2.0 Reference Design
frames in the Schedule table have been transmitted, the
next cycle starts again from the first frame of the table.
The LIN 2.0 API has many functions to manage the Sched-
ule table. It has functions to select tables, to initiate the
transfer of the next frame in the current table, and so on.
More details on these APIs are found in section 3,
Design APIs, on page
Figure 2-5. Hardware Configuration of a LIN Master/Slave
2.4
Figure 2-5 shows the hardware architecture for the LIN Mas-
ter/Slave.
2.4.1
Because the physical LIN bus is held at Vbat in the range of
8 to 18 volts, a LIN transceiver device is required to connect
the LIN bus with the PSoC chip. The LIN transceiver con-
verts the single wire LIN bus at 8V – 18 volts to TTL-level TX
and RX signals, which can be connected to the PSoC.
2.4.2
You must use a voltage regulator to provide the PSoC Vcc
supply. LIN transceivers with built-in regulators are avail-
able.
2.4.3
You have the option to decide which pins to use for the TX
and RX pins in the design. These connections are done in
the Device Editor of PSoC Designer. Details on how to con-
figure the pins are in section 5,
page
October 25, 2006
35.
Hardware Architecture
LIN Transceiver
Voltage Regulator
External Pin Connections
25.
Using the Design IP, on
Cypress Semiconductor – Rev. **
Master
2. System Architecture
13