M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 57

• Manufacturer Part Number: M5249C3
• Description: KIT EVAL FOR M5249 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5249C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5249
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MCF5249
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 3
Hardware Description and Reconfiguration
This chapter provides a functional description of the M5249C3 board hardware. With the description
given here and the schematic diagrams in
understanding of the board's design. In this manual, an active low signal is indicated by a bar over the
signal name.
3.1
This part of the chapter discusses the CPU and general support logic on the M5249C3 board.
3.1.1
The microprocessor used on the M5249C3 is the highly integrated ColdFire MCF5249, 32-bit processor.
The MCF5249 implements a ColdFire Version 2 core with 8-KByte instruction cache, two UART
channels, two timers, 96-KBytes of SRAM, a QSPI (Queued Serial Peripheral Interface) module, an I
module, 4x I
multiplexed with other signals) and the system integration module (SIM). All of the core processor
registers are 32 bits wide except for the Status Register (SR) which is 16 bits wide. This processor
communicates with external devices over a 16-bit wide data bus, D[31:16]. The chip can address
64-MBytes of memory space using a 25-bit wide address bus and internal chip-select logic. All the
processor's signals are available through the expansion connectors (J4 and J5). Refer to
“Expansion Connectors - J4 and J5,”
The MCF5249 processor has the capability to support both an IEEE JTAG-compatible port and a BDM
debug port. These ports are multiplexed and can be used with third party tools to allow the user to
download code to the board. The board is configured to boot up in the normal/BDM mode of operation.
The BDM signals are available at port (J2). The processor also has the logic to generate up to four (4) chip
selects, CS0 to CS3, and support for 2 banks of SDRAM (included on the evaluation board as 8-Mbytes
in total configured as 4Mx16). The SDRAM_CS1 signal is used to provide selection and control of this
bank of SDRAM.
3.1.2
The reset logic provides system initialisation. Reset occurs during power-on or via assertion of the signal
RESET which causes the MCF5249 to reset. Reset is also triggered by the reset switch (S1) which resets
the entire processor/system.
A hard reset and voltage sense controller (U9) is used to produce an active low power-on RESET signal.
The reset switch S1 is fed into U9 which generates the signal which is fed to the MCF5249 reset, RESET.
Freescale Semiconductor
The Processor and Support Logic
Processor
Reset Logic
2
S modules, an IDE module, a Flash memory stick interface, 64 parallel I/O ports (which are
for their pin assignments.
M5249C3 User’s Manual, Rev. 1
Appendix C, “Schematics,”
the user can gain a good
Section 3.3.1,
2
3-1
C