M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 60

• Manufacturer Part Number: M5249C3
• Description: KIT EVAL FOR M5249 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5249C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5249
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MCF5249
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hardware Description and Reconfiguration
The M5249C3 uses the following signals to select external peripherals:
The chip select mechanism of the MCF5249 processor allows the memory mapping to be defined for the
required memory space (User/Supervisor, Program/Data spaces).
All of the MCF5249 internal registers, configuration registers, parallel I/O port registers, UART registers
and system control registers are mapped by the MBAR register at any 1-KByte boundary. The MBAR1
register is mapped to 0x1000_0000 and MBAR2 mapped to 0x8000_0000 by the dBUG monitor. For a
complete map of these registers refer to the MCF5249 User's Manual.
The M5249C3 board has 8-MBytes of SDRAM installed. Refer to
discussion of the SDRAM on the board. The dBUG ROM monitor is programmed in one AMD
Am29LV160DB-90 Flash ROM which occupies 2-MBytes of the address space. The first 256-KBytes, i.e
the first sector, are used by ROM Monitor and the remainder is left for the user. Refer to
“Flash ROM.”
Table 3-1
All of the unused area of the memory map is available to the user.
3.1.9
After reset, the processor attempts to read the initial stack pointer and program counter values from
locations $00000000 & $00000004 (the first eight bytes of memory space). This requires the board to have
a non-volatile memory device in this range with the correct information stored in it. In some systems,
however, it is preferred to have RAM starting at address $00000000. The MCF5249 processor chip-select
zero (CS0) responds to any accesses after reset until the CSMR0 is written. Since CS0 (the global chip
select) is connected to the Flash ROM (U6), the Flash ROM initially appears at address $00000000 which
provides the initial stack pointer and program counter (the first eight bytes of the Flash ROM). The
3-4
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$8000_0000 – $BFFF_FFFF MBAR2—Module Base Address Reg. 2
$FFE0_0000 – $FFFF_FFFF CS0, 2M Flash ROM
$0002_0000 – $007F_FFFF SDRAM space
$2000_0000 – $2000_FFFF SRAM1
$3000_0000 – $3007_FFFF CS1, External Ethernet controller
$1000_0000 – $1000_03FF System Integration Module (SIM) registers
$2001_0000 – $2001_7FFF SRAM0
$0000_0000 – $0002_0000 SDRAM space for dBug ROM monitor use
$1000_0000 – $1000_0054 MBAR—Module Base Addres Reg.
CS0 to enable the Flash ROM (refer to
SDRAS, SDCAS and SDRAM_CS1 to enable the SDRAM (refer to
CS1 for the Ethernet controller
Address Range
shows the M5249C3 memory map.
Reset Vector Mapping
Table 3-1. M5249C3 Memory Map
M5249C3 User’s Manual, Rev. 1
Signal and Device
Section 3.1.13, “Flash
Section 3.1.12, “SDRAM,”
ROM”)
8-7-7-7
Refer to manufacturer spec.
Refer to manufacturer spec.
Internal access
Refer to MCF5249UM SIM section
Internal access (1 cycle)
Internal access (1 cycle)
Refer to MCF5249UM SIM section
8-7-7-7
Memory Access Time
Section 3.1.12,
Freescale Semiconductor
Section 3.1.13,
“SDRAM”)
for a