M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 73

• Manufacturer Part Number: M5249C3
• Description: KIT EVAL FOR M5249 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5249C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5249
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MCF5249
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Appendix B
PAL Equations
The PAL equations listed below provide simple logic equations for the memory mapped interface to the
Ethernet controller U4 (sheet 5 of the schematics). The first equation inverts the interrupt signal from the
LAN91C111 and generates an IRQ6 signal to the MCF5249. The next equation inverts the R/W signal
from the MCF5249 to create the W/R signal required by the Ethernet controller. The next two equations
create the positive read (RD) and write (WR) control signals required by the LAN91C111 using the R/W
and CS1 signals from the MCF5249. Finally the reset logic of the LAN91C111 requires a positive logic
RESET signal which is a simple inversion of RESET signal applied to the MCF5249 from either the BDM
port, reset switch (S1) or power on reset (POR).
Important Note the
an asynchronous TA terminated interface was considered for the ethernet controller, which is why these
signals have been brought out to the PAL. After initial debug of the board a simple asynchronous
auto-acknowledge interface with wait states set up in the chip select control register sufficed.
module EthernetIF
title 'Ethernet Interface logic for the M5249C3 board'
"March 2 2002 Revision 1.0 of the code"
"EthernetIF device 'ispLSI22LV10';
;"*****************************************************"
;"This abel file contains the code to interface the SMSC"
;"10/100baseT Ethernet controller LAN91C111-NE to the"
;"MCF5249 ColdFire processor"
;"It was targeted to Lattice ispLSI 22LV10 PAL"
;"CS:380E "
;"*****************************************************"
;"*****************************************************"
;"Declaration Section
;"*****************************************************"
" Inputs
BCLK
RESET
!CS1
R_W
"!TA_IN
"!OE
"!SRDY
INTR0
"ARDY
" Outputs
"!ANRDYREG
Freescale Semiconductor
"
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
symbol at the start of some of the signal definitions comments out the signal. Intially
2;
3;
4;
5;
6;
7;
9;
10;
11;
17 ISTYPE 'reg';
M5249C3 User’s Manual, Rev. 1
" Bus clock input to the 22V10 from MCF5249
" /RESET Input from MCF5249
" /CS1 Chip Select 1 input from MCF5249
" Read not Write input from MCF5249
"" /TA Transfer Ack. input from expansion
connector
"" /OE Output Enable input from MCF5249
"" /SRDY Synchronous Ready input from LAN91C111
" Interrupt 0 input from LAN91C111
"" ARDY Asynchronous ready input from LAN91C111
"" Registered ARDY
"
B-1