M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 62

• Manufacturer Part Number: M5249C3
• Description: KIT EVAL FOR M5249 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5249C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5249
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MCF5249
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hardware Description and Reconfiguration
3.1.14
Jumper 12 allows users to test code from boot/POR without having to overwrite the ROM Monitor.
When the jumper is set between pins 1 and 2, the behavior of the system is normal, dBUG boots and then
runs from 0xFFE00000. When the jumper is set between pins 2 and 3, the board boots from the second
half of the Flash (0xFFF00000).
Procedure:
3.2
The M5249C3 offers two serial communications channels. They are discussed in this section.
3.2.1
The MCF5249 device has two built in UARTs, each with its own software programmable baud rate
generators. One channel is the ROM Monitor to Terminal output and the other is available to the user. The
ROM Monitor programs the interrupt level for UART0 to Level 3, priority 2 and autovector mode of
operation. The interrupt level for UART1 is programmed to Level 3, priority 1 and autovector mode of
operation. The signals from these channels are available on expansion connector (J5). The signals of
UART0 and UART1 are also passed through the RS-232 driver/receivers (U13) & (U14) and are available
on DB-9 connectors (P3) and (P4). Refer to the MCF5249 User’s Manual for programming the UART’s
and their register maps.
3.2.2
The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheral interface with queued
transfer capability. It will support up to 16 stacked transfers at one time, minimising CPU intervention
between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.
Functionality is very similar, but not identical, to the QSPI portion of the QSM (Queued Serial Module)
implemented in the MC68332 processor.
3-6
1. Compile and link as though the code was to be placed at the base of the flash, but setup so that it
2. Set up the jumper (JP12) for Normal operation, pin1 connected to pin 2.
3. Download to SDRAM (If using serial or ethernet, start the ROM Monitor first. If using BDM via
4. In the ROM Monitor, execute the 'upuser' command.
5. Move jumper (JP12) to pin 2 connected to pin 3 and push the reset button (S1). User code should
•
•
will download to the SDRAM starting at address 0xE0000. The user should refer to their compiler
documentation for this, since it will depend upon the compiler used.
a wiggler cable, download first, then start ROM Monitor by pointing the program counter (PC) to
0x7FE00400 and run.)
now be running from reset/POR.
Programmable queue to support up to 16 transfers without user intervention
Supports transfer sizes of 8 to 16 bits in 1-bit increments
Serial Communication Channels
JP12 Jumper and the User’s Program
MCF5249 UARTs
QSPI Module
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor