M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 107

IC M16C MCU FLASH 48K 48LQFP

M30260F6AGP#U5A

Manufacturer Part Number
M30260F6AGP#U5A
Description
IC M16C MCU FLASH 48K 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet

Specifications of M30260F6AGP#U5A

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
UART
Total Internal Ram Size
2KB
# I/os (max)
39
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
R8C
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
39
Number Of Timers
8
For Use With
R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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Quantity
Price
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Manufacturer:
Renesas Electronics America
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Renesas Electronics America
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Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
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Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
R
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1
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Figure 11.1.1 Transfer Cycles for Source Read
0
6
2
9
C
0 .
B
2 /
0
0
2
6
0
A
F
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address
(3) When the source read cycle under condition (1) has one wait state inserted
(4) When the source read cycle under condition (2) has one wait state inserted
NOTE:
2
CPU clock
CPU clock
CPU clock
CPU clock
e
Address
bus
RD signal
WR signal
Data
bus
Address
bus
RD signal
WR signal
Data
bus
Address
bus
RD signal
WR signal
Data
bus
Address
bus
RD signal
WR signal
Data
bus
0 -
G
b
1. The same timing changes occur with the respective conditions at the destination as at the source.
1 .
2
o r
0
, 5
u
0
p
2
0
(
M
0
7
1
CPU use
6
CPU use
CPU use
C
page 88
CPU use
CPU use
CPU use
CPU use
CPU use
2 /
6
, A
M
1
f o
6
3
C
Source
Source
2
2 /
9
6
Source
Source
Source
, B
Source
Source + 1
M
Source
Source
1
Destination
6
Source + 1
C
2 /
Destination
6
) T
Destination
Destination
Source + 1
Destination
Destination
Source + 1
Dummy
cycle
Dummy
cycle
Dummy
cycle
Dummy
cycle
Destination
Dummy
cycle
Dummy
cycle
Destination
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
Dummy
cycle
Dummy
cycle
CPU use
CPU use
11. DMAC

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