M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 184

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

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Table 13.1.3.2.1. STSPSEL Bit Functions
Figure 13.1.3.2.1. STSPSEL Bit Functions
0
Function
Output of SCL2 and SDA2 pins
C
2
9
Start/stop condition interrupt
request generation timing
0 .
B
2 /
0
0
6
13.1.3.3 Arbitration
2
A
0
Unmatching of the transmit data and SDA
edge of SCL
U2RB register is updated. If the ABC bit is set to "0" (updated bitwise), the ABT bit is set to “1” at the
same time unmatching is detected during check, and is cleared to “0” when not detected. In cases
when the ABC bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to
“1” (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be
updated bytewise, clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte,
before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDA
is set to “1” (unmatching detected).
F
2
e
G
(1) In slave mode,
STPSEL bit
SCL2
SDA2
(2) In master mode,
STPSEL bit
SCL2
SDA2
0 -
b
o r
1 .
2
Set STAREQ to "1" (start)
CKDIR is set to "1" (external clock)
CKDIR is set to "0" (internal clock), CKPH is set to "1"(clock delayed)
0
, 5
u
0
p
2
(
0
M
0
7
1
6
2
. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the
C
page 165
0
2 /
6
, A
Start condition detection
interrupt
Set to "1" by
a program
M
1
f o
6
C
3
2
2 /
9
2
6
Start condition detection
interrupt
1st
, B
pin is placed in the high-impedance state at the same time the ABT bit
STSPSEL = 0
Output transfer clock and data/
Program with a port determines
how the start condition or stop
condition is output
Start/stop condition are de-
tected
Set to "0" by
a program
M
2nd
1
1st
6
C
3rd
2nd
2 /
4th
6
) T
2
3rd
pin input data is checked synchronously with the rising
4th
5th
6th
5th
7th
6th
Set STPREQ
to "1" (start)
8th
7th
Stop condition detection
interrupt
9th bit
8th
STSPSEL = 1
The STAREQ, RSTAREQ and
STPREQ bit determine how the
start condition or stop condition is
output
Start/stop condition generation are
completed
Set to "1" by
a program
9th bit
Stop condition detection
interrupt
Set to "0" by
a program
13. Serial I/O