M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 61

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

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1
Figure 7.5. CM2 Register
0
6
2
9
C
0 .
B
Oscillation stop detection register (1)
2 /
0
0
b7
2
NOTES:
6
0
F
A
2
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
2. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to
3. If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock not oscillating), do not set the CM21 bit to “0”.
4. This flag is set to “1” when the main clock is detected to have stopped or when the main clock is detected to
5. Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main
6. Effective when the CM07 bit in the CM0 register is set to “0”.
7. When the PM21 bit in the PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no effect.
8. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to “1”
9. Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back to "1”
10. Set the CM20 bit to “0” (disable) before setting the CM05 bit in the CM0 register.
11. The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
12. When the CM21 bit is set to "0" (on-chip oscillator turned off) and the CM05 bit is set to "1" (main clock turned off), the
e
b6
0 -
b
G
“1”(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit
isautomatically set to “1” (on-chip oscillator clock) if the main clock stop is detected.
haverestarted oscillating. When this flag changes state from “0” to “1”, an oscillation stop, reoscillation detection interrupt
isgenerated. Use this flag in an interrupt routine to discriminate the causes of interrupts between theoscillation
stop,reoscillation detection interrupts and the watchdog timer interrupt. The flag is cleared to “0” by writing a “0” in
aprogram. (Writing a “1” has no effect. Nor is it cleared to “0” by an oscillation stop or an oscillation restart
detectiointerrupt request acknowledged.) If when the CM22 bit is set to "1" an oscillation stop or an oscillation restart is
detected, no oscillation stop, reoscillation detection interrupts are generated.
clockstatus.
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to “1” (the CPU clock source is PLL clock), the
CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is set to “0” under these conditions,
oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore, necessary to set the
CM21 bit to “1” (on-chip oscillator clock) inside the interrupt routine.
(enable).
CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).
1 .
2
0 0
o r
b5
0
, 5
0
u
b4
2
p
0
(
0
M
b3
7
1
6
b2
C
page 42
2 /
b1
6
b0
, A
M
Bit symbol
f o
1
(b5-b4)
CM20
CM21
CM22
CM23
(b6)
CM27
6
3
C
Symbol
CM2
2
9
2 /
6
, B
M
System clock select bit 2
Oscillation stop, re-
oscillation detection flag
Oscillation stop, re-
oscillation detection bit
(7, 9, 10, 11)
Reserved bit
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
X
(2, 3, 6, 8, 11, 12 )
Operation select bit
(when an oscillation stop,
re-oscillation is detected)
(11)
(4)
(5)
IN
1
6
monitor flag
C
Bit name
2 /
6
) T
Address
000C
16
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
0: Oscillation stop, re-oscillation
1: Oscillation stop, re-oscillation
0: Main clock or PLL clock
1: On-chip oscillator clock
0: Main clock stop or re-oscillation
1: Main clock stop or re-oscillation
0: Main clock oscillating
1: Main clock not oscillating
Must set to “0”
detection interrupt
(On-chip oscillator oscillating)
not detected
detected
detection function enabled
detection function disabled
0X000010
After reset
Function
2
(11)
7. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RO