M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 115

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

M
R
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E
1
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J
6
Figure 12.1.4. ONSF Register, TRGSR Register, and CPSRF Register
0
C
2
9
2 /
0 .
B
0
0
6
2
A
0
F
2
G
e
One-shot start flag
0 -
Clock prescaler reset flag
b7
Trigger select register
b
b7
b7
NOTES:
o r
NOTES:
1 .
2
u
0
1. Make sure the port direction bits for the TA1
2. Overflow or underflow.
b6
b6
b6
, 5
1. Make sure the PD7_1 bit in the PD7 register is set to “0” (= input mode).
2. Overflow or underflow.
0
p
2
b5
b5
b5
(
0
M
0
b4
b4
b4
1
7
6
C
b3
b3
b3
2 /
page 96
b2
b2
b2
6
, A
b1
b1
b1
M
b0
b0
b0
1
f o
6
Bit symbol
Bit symbol
Bit symbol
C
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
TAZIE
TA0TGL
TA0TGH
TA1TGH
TA2TGH
TA3TGH
TA4TGH
TA1TGL
TA2TGL
TA3TGL
TA4TGL
(b6-b0)
3
CPSR
2 /
2
Symbol
TRGSR
Symbol
CPSRF
9
Symbol
ONSF
6
, B
M
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
Z-phase input enable bit
Timer A0 event/trigger
select bit
Clock prescaler reset flag
Timer A1 event/trigger
select bit
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
Nothing is assigned.
When write, set to “0”. When read, their contents are
indeterminate.
1
6
C
Address
2 /
0383
Address
Address
0382
0381
6
Bit name
) T
Bit name
Bit name
16
IN
16
16
to TA4
IN
pins are set to “0” (= input mode).
0XXXXXXX
After reset
After reset
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, its content is “0”.)
After reset
0 : Z-phase input disabled
1 : Z-phase input enabled
b7 b6
0 0 : Input on TA0
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
b1 b0
b3 b2
b5 b4
b7 b6
0 0 :
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
0 0 :
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 :
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 :
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
00
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits in the TAiMR register
(i = 0 to 4) is set to ‘10
shot timer mode) and the MR2 bit
in the TAiMR register is set to “0”
(=TAiOS bit enabled). When read,
its content is “0”.
00
16
16
Input on TA1
Input on TA2
Input on TA3
Input on TA4
2
Function
Function
Function
IN
IN
IN
IN
IN
is selected (1)
is selected (1)
is selected (1)
is selected (1)
is selected
2
’ (= one-
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
12. Timer