M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 99

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

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10. Watchdog Timer
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Figure 10.1. Watchdog Timer Block Diagram
0
6
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer
period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that
the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start
counting by writing to the WDTS register.
Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the
beginning of the watchdog timer interrupt routine.
In stop mode, wait mode and when erase/program opration is excuting in EW1 mode without erase suspend
requeired, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the
modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers.
2
The watchdog timer is the function that detects when a program is out of control. Use the watchdog timer is
recommended to improve reliability of the system. The watchdog timer contains a 15-bit counter which is
decremented by the CPU clock that the prescaler divides. The PM12 bit in the PM1 register determines whether
to generate a watchdog timer interrupt request or reset the watchdog timer when the watchdog timer underflows.
The PM12 bit can only be set to “1” (reset). Once the PM12 bit is set to “1”, it cannot be changed to “0” (watchdog
timer interrupt) by program. Refer to “5.3 Watchdog Timer Reset” for watchdog timer reset.
When the main clock, on-chip oscillator clock, or PLL clock runs as CPU clock, the WDC7 bit in the WDC register
determines whether the prescaler divides the clock by 16 or 128. When the sub clock runs as CPU clock, the
prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calculated as
follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
9
C
With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock
Watchdog timer period =
With sub-clock chosen for CPU clock
Watchdog timer period =
0 .
B
2 /
Internal reset signal
(low active)
0
CPU clock
0
2
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0
A
F
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0 -
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Write to WDTS register
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p
2
0
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0
7
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page 80
2 /
On-chip oscillator clock
6
, A
Prescaler
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1/128
1/16
1/2
1
f o
6
Prescaler dividing (2) X Watchdog timer count (32768)
3
C
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
2
2 /
9
CM07 = 0
WDC7 = 1
CM07 = 1
CM07 = 0
WDC7 = 0
6
, B
M
1
6
C
2 /
6
PM22 = 0
PM22 = 1
) T
CPU clock
CPU clock
Watchdog timer
Set to 7FFF
16
PM12 = 0
PM12 = 1
10. Watchdog Timer
Reset
Watchdog timer
interrupt request