M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 199

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

M
R
R
14. A/D Converter
e
E
1
. v
J
6
Table 14.1 A/D Converter Performance
NOTES:
0
C
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10
AN
using these inputs, make sure the corresponding port direction bits are set to “0” (input mode).
When not using the A/D converter, set the VCUT bit to “0” (V
from the V
The A/D conversion result is stored in the i bits in the A/D register for AN
Table 14.1 shows the A/D converter performance. Figure 14.1 shows the A/D converter block diagram
and Figures 14.2 to 14.4 show the A/D converter associated with registers.
A/D Conversion Method
Analog Input Voltage
Operating Clock fAD
Resolution
Integral Nonlinearity Error When AV
Operating Modes
Analog Input Pins
Conversion Speed Per Pin
2
9
2 /
0 .
B
Note
Do not use P9
1. Not dependent on use of sample and hold function.
2. Set the AD frequency to 10 MHz or less. For M16C/26B, set it to 12 MHz or less.
P9
0
0
6
7
2
), P9
A
0
2
F
2
Without sample-and-hold function, set the fAD frequency to 250kH
With the sample and hold function, set the fAD frequency to 1MH
G
e
and P9
0 -
b
o r
0
1 .
2
Item
u
0
REF
to P9
, 5
0
p
2
(
0
3
M
pin into the resistor ladder, helping to reduce the power consumption of the chip.
0
(AN
3
1
2
7
6
(AN3
and P9
(3)
C
(2)
page 180
(1)
32
2 /
, AN
6
0
, A
to AN3
3
24
M
(AN
Successive approximation (capacitive coupling amplifier)
0V to AV
f
or f
8-bit or 10-bit (selectable)
• With 8-bit resolution: 2LSB
• With 10-bit resolution: 3LSB
When AV
• With 8-bit resolution: 2LSB
• With 10-bit resolution: 5LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
8 pins (AN
8 pins (AN
• Without sample and hold function
• With sample and hold function
) are not available in the 42-pin package.
1
AD
8-bit resolution: 49 f
8-bit resolution: 28 f
f o
6
32
C
/divided-by-2 or f
AD
2
3
2 /
, AN2
2
, AN
/divided-by-12 or f
9
6
, B
CC
24
CC
CC
4
0
0
M
) as analog input pins in the 42-pin package.
). Similarly, AD
(V
to AN
to AN
1
= V
= V
6
CC
C
REF
REF
2 /
)
7
7
6
) + 3 pins (AN
) + 2 pins (AN
) T
AD
= 5V
= 3.3V
AD
AD
/divided-by-3 or f
___________
AD
cycles, 10-bit resolution: 59 f
cycles, 10-bit resolution: 33 f
TRG
input shares the pin with P1
Performance
REF
30
30
, AN
to AN
unconnected), so that no current will flow
31
AD
32
)
/divided-by-4 or f
) + 1 pins (AN
Z
i
Z
, AN
or more.
or more.
3i
, and AN
AD
AD
cycles
cycles
24
AD
) (48-pin package)
5
. Therefore, when
2i
(42-pin package)
0
/divided-by-6
pins (i = 0 to 7).
to P10
14. A/D Converter
7
(AN
0
to