MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1089

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Appendix A
MPC562/MPC564 Compression Features
The MPC562/MPC564 contains a number of code compression features not found in the
MPC561/MPC563 that function from the burst buffer controller module (BBC) module of the device.
The BBC’s instruction code decompressor unit (ICDU) is responsible for on-line (previously compressed)
instruction code decompression in the decompression on mode. The ICDU contains a 2-Kbyte RAM
(DECRAM) that is used for decompressor vocabulary table storage when compression is enabled or as
general-purpose memory on the U-bus when compression is disabled.
A.1
The following are instruction code decompression unit key features:
A.2
The operational model used by the MPC562/MPC564 is explained in the sections below.
A.2.1
Freescale Semiconductor
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Instruction code on-line decompression is based on an “instruction class” algorithm.
There is no need for address translation between compressed and non-compressed address spaces
— ICDU provides the “next instruction address” to the RCPU.
In most cases, instruction decompression takes one clock.
Code decompression is pipelined:
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Two operation modes are available: decompression on and decompression off. Switches between
compressed and non-compressed user application software is possible.
Adaptive vocabularies scheme is supported; each user application can have its own optimum
vocabularies.
Implemented for MPC56x architecture
Up to 50% instruction code size reduction
No need for address translation tables
ICDU Key Features
Class-Based Compression Model Main Principles
Compression Model Features
The code compression features of the MPC562/MPC564 are different than
the code compression of the MPC556.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
A-1