MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1095

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

A.2.7
A.2.8
The bypass field can be either a full bypass, (i.e., the whole segment from the un-compressed instruction
appears as is in the compressed instruction), or it can be represented in one of several compression
encoding formats. These formats are hard-wired in the decompression module.
A.2.8.1
For the MPC562/MPC564, a 15-bit bypass is used to indicate that the AA bit of a branch instruction should
be inserted with a value of zero. The decompression process is performed as shown in
This bypass is coded by a value of “13” (0xD) in the TP2LEN field of the DCCR register.
Freescale Semiconductor
15-bit Compressed
Bypass Field
Decompressed
Right Segment
•
•
•
•
•
•
•
•
•
•
Compressed instruction length may vary between 6 and 36 bits and is even.
A compressed instruction can begin at any even location in a memory word.
An instruction source may be compressed as a single 32-bit segment or as two independent 16-bit
segments.
Possible partitions of an instruction for compression are:
A bypass field is always the second field of the two possible. Length of a bypass field can be zero,
10, 15, 16 or 32 bits.
The class prefix in a compressed instruction is 4 bits long and covers up to 16 classes.
The vocabulary table pointer of each field may be 2 to 9 bits long.
Vocabulary table pointers are reversed in the code. This means the pointer’s LSB will be the first
bit.
In a class with a single segment of full compression, data is fetched from both memories.
Every vocabulary table in the DECRAM is 16 bytes (8 entries) aligned (3 LSBs zeroed).
– One 32-bit bypass segment
– One 32-bit compressed segment
– One 16-bit compressed segment and one 16-bit bypass segment
– Two 16-bit compressed segments
Class Code Compression Algorithm Rules
Bypass Field Compression Rules
Branch Right Segment Compression #1
0
16
Figure A-4. Branch Right Segment Compression #1
MPC561/MPC563 Reference Manual, Rev. 1.2
MPC562/MPC564 Compression Features
13 14
29 30
0
LK
31
Figure
A-4.
A-7