MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 401
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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a 16-bit boot EPROM and CS1 is used for a 32-bit SRAM. The WE/BE[0:3] signals are used both to
program the EPROM and to enable write access to various bytes in the RAM.
10.2
The memory controller consists of a basic machine that handles the memory access cycle: the
general-purpose chip-select machine (GPCM).
When any of the internal masters request a new access to external memory, the address of the transfer (with
17 bits having a mask) and the address type (with three bits having a mask) are compared to each one of
the valid banks defined in the memory controller. Refer to
Freescale Semiconductor
Memory Controller Architecture
MPC500
WE/BE[0:3]
Figure 10-3. MPC561/MPC563 Simple System Configuration
Address
Data
CS0
CS1
OE
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure
[0:31]
[0:15]
10-4.
Address
WE/BE[0:1]
DATA[0:15]
Address
CE
WE/BE[0:3]
Data
OE
CE
OE
EPROM
SRAM
Memory Controller
10-3
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