MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 239

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Table 5-3
master, accessing an MPC500 SPR, address bits [0:17] and [28:31] are compared to zeros to confirm that
an SPR access is valid. See
Freescale Semiconductor
.
shows the MPC561/MPC563 address format for special purpose register access. For an external
1
Address[0:31]
Bits [0:17] and [28:31] are all 0.
Internal
0x2C00
0x3D30
0x1A80
0x3A80
0x1880
0x3880
Section 6.1.2.1, “Operation in External Master
Decrementer (DEC).
See
(DEC),” for more information.
Time Base Lower — Read (TBL).
See
for bit descriptions.
Time Base Upper — Read (TBU).
See
for bit descriptions.
Time Base Lower — Write (TBL).
SeeSee
(TB),” for bit descriptions.
Time Base Upper — Write (TBU).
See
for bit descriptions.
Internal Memory Mapping Register (IMMR).
See
Table 5-3. Hex Address Format for SPR Cycles
A[0:17]
Table 5-2. USIU Special-Purpose Registers
Section 3.9.5, “Decrementer Register
Section 6.2.2.4.2, “Time Base SPRs
Section 6.2.2.4.2, “Time Base SPRs
Section 6.2.2.4.2, “Time Base SPRs
Table 6-12
MPC561/MPC563 Reference Manual, Rev. 1.2
0
Section 6.2.2.4.2, “Time Base SPRs
for bit descriptions.
A[18:22]
Register
spr5:9
A[23:27]
spr0:4
(TB),”
(TB),”
(TB),”
A[28:31]
Unified System Interface Unit (USIU) Overview
0
Decimal Address
spr[5:9]:spr[0:4]
Modes,” for more details.
268
269
284
285
638
22
1
5-7