MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1417

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

SS 15-42
SS 15-39
SSE1 13-16
SSE2 13-18
Standard
standby operation 22-5
Star-point ground system 13-70
Start
State machine 13-47
Status register (QASR) 13-8
STF 19-11
STOP 13-8
Stop
storage control instructions, 3-45
storage reservation, 9-42
Stress conditions 13-76
STUFFERR 16-34
Subqueue 13-38
Substitute remote request field (SRR) 16-6
Successive approximation register (SAR) 13-37
Summary overflow 3-18
Supervisor
Supervisor mode
SUPV 13-9
SUSG 23-48
SUSH 23-48
SWSR 6-38
SWT 6-21
Synchronized pulse-width modulation (SPWM) D-48
SYPCR 6-37
SYSE 23-42
SYSEE 23-44
System call exception 3-54
system clock output, 9-8
system reset exception 3-45
Freescale Semiconductor
message format 16-1
bit (beginning of data frame) 15-51
-of-frame (SOF) symbol 16-10
clocks to TCRs (CLKS) 19-12
enable (STOP) 13-8
enable (STOP) bit
flag (STF) 19-11
mode 13-9
SCI end of data frame bit 15-51
/Unrestricted data space (SUPV) 13-9
/unrestricted data space (SUPV)
and SRAM 15-9
frames 16-4
QSM 15-6
TOUCAN 16-18
TPU 19-11
TPU 19-11
,
,
,
,
13-9
13-11
,
14-17
14-19
14-8
,
,
14-39
14-8
,
14-8
,
14-48
,
,
14-8
,
16-18
,
14-74
14-10
,
,
15-57
13-20
,
19-11
,
14-68
,
14-7
MPC561/MPC563 Reference Manual, Rev. 1.2
,
,
14-8
14-22
,
14-38
system reset interrupt, 3-45
T
T1 13-54
T2 13-54
T2CFILTER 19-20
T2CG 19-7
T2CLK pin filter control (T2CFILTER) 19-20
T2CSL 19-12
TA 9-6
Table stepper motor (TSM) D-7
TAP controller 25-4
TB 6-19
TB register 3-23
TBREF registers 6-41
TBRS1, TBRS0 - bits in BIUMCR 17-13
TBSCR 6-42
TBSPR 6-40
TC 15-49
TCIE 15-47
TCNMCR 16-25
TCODE 24-4
TCR1P 19-11
TCR2 clock/gate control (T2CG) 19-11
TDRE 15-49
TE 15-46
TEA 9-6
termination signals, 9-40
TESR 6-39
test register (DPTTCR) 20-4
Test register (QADCTEST) 13-7
TICR 19-14
TIE 15-47
Time
time base (TB) 6-19
time base bus
time base register (TB) 3-23
timebase register 3-44
TIMER 16-31
Timer
Timing, instruction 3-37
tool-mapped registers 24-9
TOR 13-55
TOR1 13-23
TOR2 13-24
TOUCAN
quanta clock 16-8
stamp 16-4
selecting 17-13
count register
synchronize mode (TSYNC) 16-29
1 prescaler control (TCR1P) 19-11
,
9-40
,
,
,
,
,
9-40
14-53
14-53
,
15-48
15-54
,
15-55
,
,
,
19-11
14-54
,
,
15-55
19-21
,
14-24
14-25
16-12
,
6-40
Index-17