MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1150
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Clock and Board Guidelines
C.2.3
C
The maximum noise allowed on XFC is 50 mV peak-to-peak with a typical cut-off frequency of 500 Hz.
The XFC capacitor creates a low pass filter in the PLL loop. The filter output feeds the PLL VCO. The
capacitor is charged and discharged by short current pulses, generated by the phase detector. So the
capacitor leakage and absorption directly affect the AC component in the VCO input voltage that creates
PLL output clock jitter. Therefore, the dielectric quality of C
Smaller C
but slower to gain lock. Because each board layout and application is unique, C
a system.
The minimum required value (including capacitor tolerance) for C
cases:
C-6
XFC
is the PLL feedback capacitor. It must be located as close as possible to the XFC and VDDSYN pads.
0 < (MF+1) < 4
(MF+1) >= 4
XFC
PLL Off-Chip Capacitor C
makes the PLL faster to gain lock but less stable. Higher C
Note: A filter cut off frequency of 500Hz is recommended, however this will result in a
capacitor size of 33uF using a 10 Ohm resistor. This may be too expensive or large
for the system. In this case the filter shown with cut- off frequency of 160kHz will suffice.
Note: A filter cut off frequency of 500Hz is recommended, however this will result in a
capacitor size of 15uF using a 8.2mH inductor. This may be too expensive or large
for the system. In this case the filter shown with cut- off frequency of 5.5kHz will suffice.
Keyed
VDD 2.6 V
Keyed
VDD 2.6 V
Figure C-7. LC Filter Example (Alternative)
MPC561/MPC563 Reference Manual, Rev. 1.2
8.2 mH
Board
Board
10 Ω
Figure C-6. RC Filter Example
100 nF
100 nF
VSSSYN
VSSSYN
XFC
C
C
XFC
XFC
= (2100 * (MF+1)) pF
= (1130 * (MF+1) – 80) pF
MPC56x Device
MPC56x Device
XFC
VDDSYN
XFC
VDDSYN
should be high.
is determined by the following two
XFC
makes the PLL more stable
XFC
must be evaluated in
Freescale Semiconductor
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