MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 821
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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18.4.3
The two transmit configuration registers control which internal modules will transmit data through the
PPM. Each of the configuration registers contains eight separate 2-bit wide bit fields. Each of the 16 fields
controls a multiplexer that selects a 1-bit channel from an internal module to the PPM transmit data
register. See
Freescale Semiconductor
PPM_TSYNC
PPM_TSYNC
PPM_TCLK
PPM_TCLK
PPM_TCLK
PPM_TCLK
PPMPCR[CM]
DATA
DATA
Transmit Configuration Registers (TX_CONFIG_1 and
TX_CONFIG_2)
Table 18-6
X
0
0
1
CI = 0
CI = 1
CI = 0
CI = 1
Table 18-5. PPMPCR[CM] and PPMPCR[STR] Bit Operation
for more information on channel control and setting the channel values.
PPMPCR[STR]
Figure 18-12. SPI Transfer Format with CP = 0
Figure 18-13. SPI Transfer Format with CP = 1
MPC561/MPC563 Reference Manual, Rev. 1.2
X
X
1
0
One data frame transmitted and/or received through PPM.
Transfer of one data frame completed.
Continuously transmit and/or receive data frames through PPM.
CM and STR will only effect PPM transmit/receive when PPM is
configured for SPI mode. In TDM mode transmit/receive will be
continuous regardless of the values of CM and STR bits.
Result
Peripheral Pin Multiplexing (PPM) Module
18-15
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