MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 66

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC561MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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9-6
9-7
9-8
9-9
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
12-1
12-2
12-3
12-4
12-5
12-6
12-7
13-1
13-2
13-3
13-4
13-5
13-6
lxvi
Table
Number
BURST/TSIZE Encoding ....................................................................................................... 9-38
Address Type Pins .................................................................................................................. 9-39
Address Types Definition ....................................................................................................... 9-39
Termination Signals Protocol ................................................................................................. 9-49
Timing Requirements for Reduced Setup Time ..................................................................... 10-6
Timing Attributes Summary ................................................................................................. 10-11
Programming Rules for Timing Strobes ............................................................................... 10-22
Write Enable/Byte Enable Signals Function ........................................................................ 10-24
Boot Bank Fields Values After Hard Reset .......................................................................... 10-28
Memory Controller Address Map......................................................................................... 10-31
DMBR Bit Descriptions........................................................................................................ 10-36
DMOR Bit Descriptions ....................................................................................................... 10-38
DMPU Registers ..................................................................................................................... 11-6
Reservation Snoop Support .................................................................................................... 11-9
L2U_MCR LSHOW Modes ................................................................................................. 11-10
L2U Show Cycle Support Chart ........................................................................................... 11-12
L2U (PPC) Register Decode................................................................................................. 11-12
Hex Address For SPR Cycles ............................................................................................... 11-13
STOP and HSPEED Bit Functionality.................................................................................... 12-2
Bus Cycles and System Clock Cycles .................................................................................... 12-3
ILBS Signal Functionality ...................................................................................................... 12-5
IRQMUX Functionality .......................................................................................................... 12-5
UIMB Interface Register Map ................................................................................................ 12-6
UMCR Bit Descriptions.......................................................................................................... 12-8
UIPEND Bit Descriptions....................................................................................................... 12-9
QADC64E_A Address Map ................................................................................................... 13-3
QADC64E_B Address Map.................................................................................................... 13-4
Multiplexed Analog Input Channels....................................................................................... 13-7
Analog Input Channels ........................................................................................................... 13-7
QADCMCR Bit Descriptions ................................................................................................. 13-8
QADC64E Bus Error Response............................................................................................ 13-11
MSTAT Bit Descriptions..................................................................................................... 10-32
BR0–BR3 Bit Descriptions.................................................................................................. 10-33
BRx[V] Reset Value ............................................................................................................ 10-34
OR0–OR3 Bit Descriptions ................................................................................................. 10-35
L2U_MCR Bit Descriptions ................................................................................................ 11-14
L2U_RBAx Bit Descriptions............................................................................................... 11-15
L2U_RAx Bit Descriptions ................................................................................................. 11-15
L2U_GRA Bit Descriptions................................................................................................. 11-16
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
Title
Freescale Semiconductor
Number
Page

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