MC68332ACAG16 Freescale Semiconductor, MC68332ACAG16 Datasheet - Page 127

no-image

MC68332ACAG16

Manufacturer Part Number
MC68332ACAG16
Description
IC MCU 32BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
SCI, SPI, UART
Minimum Operating Temperature
- 40 C
Controller Family/series
68K
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68332ACAG16
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MC68332ACAG16
Manufacturer:
Freescale
Quantity:
319
Part Number:
MC68332ACAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68332
USER’S MANUAL
form full duplex three-wire or half duplex two-wire transfers. A variety of transfer rate,
clocking, and interrupt-driven communication options are available.
Serial transfer of any number of bits from eight to sixteen can be specified. Program-
mable transfer length simplifies interfacing to a number of devices that require different
data lengths.
An inter-transfer delay of 17 to 8192 system clocks can be specified (default is 17 sys-
tem clocks). Programmable delay simplifies the interface to a number of devices that
require different delays between transfers.
A dedicated 80-byte RAM is used to store received data, data to be transmitted, and
a queue of commands. The CPU can access these locations directly. Serial peripher-
als can be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 16 serial transfers without CPU
intervention. Each queue entry contains all the information needed by the QSPI to in-
dependently complete one serial transfer.
A pointer identifies the queue location containing the command for the next serial
transfer. Normally, the pointer address is incremented after each serial transfer, but
the CPU can change the pointer value at any time. Multiple-task support can be pro-
vided by segmenting the queue.
The QSPI has four peripheral chip-select pins. Chip-select signals simplify interfacing
by reducing CPU intervention. If chip-select signals are externally decoded, 16 inde-
pendent select signals can be generated. Each chip-select pin can drive up to four in-
dependent peripherals, depending on loading.
Wraparound operating mode allows continuous execution of queued commands. In
wraparound mode, newly received data replaces previously received data in receive
RAM. Wraparound can simplify the interface with A/D converters by continuously up-
dating conversion values stored in the RAM.
Continuous transfer mode allows simultaneous transfer of an uninterrupted bit stream.
Any number of bits in a range from 8 to 256 can be transferred without CPU interven-
tion. Longer transfers are possible, but minimal CPU intervention is required to prevent
loss of data. A standard delay of 17 system clocks is inserted between each queue
entry transfer.
Freescale Semiconductor, Inc.
For More Information On This Product,
QUEUED SERIAL MODULE
Go to: www.freescale.com
6-5

Related parts for MC68332ACAG16