MC68332ACAG16 Freescale Semiconductor, MC68332ACAG16 Datasheet - Page 73

• Manufacturer Part Number: MC68332ACAG16
• Description: IC MCU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACAG16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, UART
• Minimum Operating Temperature: - 40 C
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.5.5.1 Bus Errors
4.5.5.2 Double Bus Faults
MC68332
USER’S MANUAL
The CPU32 treats bus errors as a type of exception. Bus error exception processing
begins when the CPU detects assertion of the IMB BERR signal (by the internal bus
monitor or an external source) while the HALT signal remains negated.
BERR assertions do not force immediate exception processing. The signal is synchro-
nized with normal bus cycles and is latched into the CPU32 at the end of the bus cycle
in which it was asserted. Because bus cycles can overlap instruction boundaries, bus
error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR detection/acknowledge is dependent upon several fac-
tors:
Because of these factors, it is impossible to predict precisely how long after occur-
rence of a bus error the bus error exception is processed.
Exception processing for bus error exceptions follows the standard exception process-
ing sequence. Refer to SECTION 5 CENTRAL PROCESSING UNIT for more informa-
tion about exceptions. However, a special case of bus error, called double bus fault,
can abort exception processing.
BERR assertion is not detected until an instruction is complete. The BERR latch is
cleared by the first instruction of the BERR exception handler. Double bus fault occurs
in two ways:
Multiple bus errors within a single instruction that can generate multiple bus cycles
cause a single bus error exception after the instruction has been executed.
• Which bus cycle of an instruction is terminated by assertion of BERR.
• The number of bus cycles in the instruction during which BERR is asserted.
• The number of bus cycles in the instruction following the instruction in which
• Whether BERR is asserted during a program space access or a data space ac-
1. When bus error exception processing begins and a second BERR is detected
2. When one or more bus errors occur before the first instruction after a RESET
3. A bus error occurs while the CPU32 is loading information from a bus error
BERR is asserted.
cess.
before the first instruction of the first exception handler is executed.
exception is executed.
stack frame during a return from exception (RTE) instruction.
The external bus interface does not latch data when an external bus
cycle is terminated by a bus error. When this occurs during an in-
struction prefetch, the IMB precharge state (bus pulled high, or $FF)
is latched into the CPU32 instruction register, with indeterminate re-
sults.
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
CAUTION
4-33