MC68332ACAG16 Freescale Semiconductor, MC68332ACAG16 Datasheet - Page 159

• Manufacturer Part Number: MC68332ACAG16
• Description: IC MCU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACAG16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, UART
• Minimum Operating Temperature: - 40 C
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.3.7 TPU Interrupts
MC68332
USER’S MANUAL
To support changing TPU application requirements, Freescale has established a TPU
function library. The function library is a collection of TPU functions written for easy as-
sembly in combination with each other or with custom functions. Refer to Freescale Pro-
gramming Note TPUPN00/D, Using the TPU Function Library and TPU Emulation
Mode for information about developing custom functions and accessing the TPU func-
tion library. Refer to the TPU Reference Manual (TPURM/AD) for more information
about specific functions.
Each of the TPU channels can generate an interrupt service request. Interrupts for
each channel must be enabled by writing to the appropriate control bit in the channel
interrupt enable register (CIER). The channel interrupt status register (CISR) contains
one interrupt status flag per channel. Time functions set the flags. Setting a flag bit
causes the TPU to make an interrupt service request if the corresponding channel in-
terrupt enable bit is set and the interrupt request level is nonzero.
The value of the channel interrupt request level (CIRL) field in TICR determines the
priority of all TPU interrupt service requests. CIRL values correspond to MCU interrupt
request signals IRQ[7:1]. IRQ7 is the highest-priority request signal; IRQ1 has the low-
est priority. Assigning a value of %111 to CIRL causes IRQ7 to be asserted when a
TPU interrupt request is made; lower field values cause corresponding lower-priority
interrupt request signals to be asserted. Assigning CIRL a value of %000 disables all
interrupts.
The CPU recognizes only interrupt requests of a priority greater than the value con-
tained in the interrupt priority (IP) mask in the condition code register. When the CPU
acknowledges an interrupt request, the priority of the acknowledged interrupt is written
to the IP mask and is driven out onto the IMB address lines.
When the IP mask value driven out on the address lines is the same as the CIRL value,
the TPU contends for arbitration priority. The IARB field in TPUMCR contains the TPU
arbitration number. Each module that can make an interrupt service request must be
assigned a unique non-zero IARB value in order to implement an arbitration scheme.
Arbitration is performed by means of serial assertion of IARB field bit values. IARB is
initialized to $0 during reset.
When the TPU wins arbitration, it must respond to the CPU interrupt acknowledge cy-
cle by placing an interrupt vector number on the data bus. The vector number is used
to calculate displacement into the exception vector table. Vectors are formed by con-
catenating the 4-bit value of the CIBV field in the TPU interrupt configuration register
with the 4-bit number of the channel requesting interrupt service. Since the CIBV field
has a reset value of %00, it must be assigned a value corresponding to the upper nib-
ble of a block of 16 user-defined vector numbers before TPU interrupts are enabled,
or a TPU interrupt service request could cause the CPU to take one of the reserved
vectors in the exception vector table.
Refer to SECTION 4 SYSTEM INTEGRATION MODULE for further information about
interrupts. For more information about the exception vector table refer to SECTION 5
CENTRAL PROCESSING UNIT.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
TIME PROCESSOR UNIT
7-5