MC68332ACAG16 Freescale Semiconductor, MC68332ACAG16 Datasheet - Page 88

• Manufacturer Part Number: MC68332ACAG16
• Description: IC MCU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACAG16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, UART
• Minimum Operating Temperature: - 40 C
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.7.4 Interrupt Processing Summary
4-48
Because the EBI manages external interrupt requests, the SIM IARB value is used for
arbitration between internal and external interrupt requests. The reset value of IARB
for the SIM is %1111, and the reset IARB value for all other modules is %0000.
Although arbitration is intended to deal with simultaneous requests of the same prior-
ity, it always takes place, even when a single source is requesting service. This is im-
portant for two reasons: the EBI does not transfer the interrupt acknowledge read cycle
to the external bus unless the SIM wins contention, and failure to contend causes the
interrupt acknowledge bus cycle to be terminated early, by a bus error.
When arbitration is complete, the module with the highest arbitration priority must ter-
minate the bus cycle. Internal modules place an interrupt vector number on the data
bus and generate appropriate internal cycle termination signals. In the case of an ex-
ternal interrupt request, after the interrupt acknowledge cycle is transferred to the ex-
ternal bus, the appropriate external device must decode the mask value and respond
with a vector number, then generate data and size acknowledge (DSACK) termination
signals, or it must assert the autovector (AVEC) request signal. If the device does not
respond in time, the EBI bus monitor asserts the bus error signal BERR, and a spuri-
ous interrupt exception is taken.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in re-
sponse to interrupt requests from external devices (refer to 4.8.3 Using Chip-Select
Signals for Interrupt Acknowledge). Chip-select address match logic functions only
after the EBI transfers an interrupt acknowledge cycle to the external bus following
IARB contention. If a module makes an interrupt request of a certain priority, and the
appropriate chip-select registers are programmed to generate AVEC or DSACK sig-
nals in response to an interrupt acknowledge cycle for that priority level, chip-select
logic does not respond to the interrupt acknowledge cycle, and the internal module
supplies a vector number and generates internal cycle termination signals.
For periodic timer interrupts, the PIRQ field in the periodic interrupt control register (PI-
CR) determines PIT priority level. A PIRQ value of %000 means that PIT interrupts are
inactive. By hardware convention, when the CPU32 receives simultaneous interrupt
requests of the same level from more than one SIM source (including external devic-
es), the periodic interrupt timer is given the highest priority, followed by the IRQ pins.
A summary of the entire interrupt processing sequence follows. When the sequence
begins, a valid interrupt service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction
boundary.
Do not assign the same arbitration priority to more than one module.
When two or more IARB fields have the same nonzero value, the
CPU32 interprets multiple vector numbers at the same time, with un-
predictable consequences.
Freescale Semiconductor, Inc.
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WARNING
USER’S MANUAL
MC68332