ST7FLITEU09M6TR STMicroelectronics, ST7FLITEU09M6TR Datasheet - Page 38

• Manufacturer Part Number: ST7FLITEU09M6TR
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: No

Supply, reset and clock management
7.4
7.4.1
Note:
Caution:
38/139
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three Reset sources as shown in
●
●
●
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The Reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic Reset sequence consists of 3 phases as shown in
●
●
●
When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 512 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte after a reset or
depending on the clock source selected before entering Halt mode or AWU from Halt mode.
Refer to
The Reset vector fetch phase duration is 2 clock cycles.
Table 8.
Figure 15. Reset sequence phases
External RESET source pulse
Internal LVD Reset (low voltage detection)
Internal WATCHDOG Reset
Active phase depending on the Reset source
256 or 512 CPU clock cycle delay (see table below)
Reset vector fetch
Figure
Table
CPU clock cycle delay
8.
External clock (connected to CLKIN pin)
16.
Internal RC oscillator
Clock source
AWURC
Active Phase
256 OR 512 CLOCK CYCLES
INTERNAL RESET
RESET
VECTOR
FETCH
Figure
ST7LITEU05 ST7LITEU09
15:
CPU clock cycle delay
Figure
512
256
16: