ST7FLITEU09M6TR STMicroelectronics, ST7FLITEU09M6TR Datasheet - Page 69

• Manufacturer Part Number: ST7FLITEU09M6TR
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: No

ST7LITEU05 ST7LITEU09
11.1.3
Note:
Figure 34. Lite timer block diagram
Functional description
The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of f
counter rolls over from 1F39h to 00h. If f
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR register.
When the timer overflows, the TBF bit is set by hardware and an interrupt request is
generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.
Watchdog
The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2ms (@
fosc = 8 MHz ), after which it then generates a reset.
To prevent this watchdog reset occuring, software must set the WDGD bit. The WDGD bit
is cleared by hardware after t
regular intervals to prevent a watchdog reset occurring. Refer to
If the watchdog is not enabled immediately after reset, the first watchdog timeout will be
shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms
period has already elapsed after the last MCU reset, the watchdog reset will take place as
soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog
immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog
reset will not occur for at least 2 ms.
Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
LTIC
f
OSC
LTICR
13-bit UPCOUNTER
INPUT CAPTURE
REGISTER
8-bit
8 MSB
7
LTCSR
WDG
ICIE
f
f
LTIMER
LTIMER
/2
. This means that software must write to the WDGD bit at
ICF
TB
1
0
OSC
To 12-bit AT TImer
f
WDG
Timebase
1 or 2 ms
(@ 8 MHz
f
OSC
TBIE
OSC
= 8 MHz, then the time period between two
)
. A counter overflow event occurs when the
TBF
WDG
RF
WATCHDOG
LTIC INTERRUPT REQUEST
LTTB INTERRUPT REQUEST
WDGE
WDGD
Figure
0
WATCHDOG RESET
On-chip peripherals
35.
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