ST7FLITEU09M6TR STMicroelectronics, ST7FLITEU09M6TR Datasheet - Page 42

• Manufacturer Part Number: ST7FLITEU09M6TR
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: No

Interrupts
8
Note:
Note:
Priority management
Interrupts and low power mode
8.1
42/139
Interrupts
The ST7 core may be interrupted by one of two different methods: Maskable hardware
interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt
(TRAP). The Interrupt processing flowchart is shown in
The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
However, disabled interrupts may be latched and processed when they are enabled (see
external interrupts subsection).
After reset, all interrupts are disabled.
When an interrupt has to be serviced:
●
●
●
●
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I bit is cleared and the main program
resumes.
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority
defines which one will be serviced first (see the Interrupt Mapping table).
All interrupts allow the processor to leave the Wait low power mode. Only external and
specifically mentioned interrupts allow the processor to leave the Halt low power mode (refer
to the “Exit from Halt” column in the Interrupt Mapping table).
Non maskable software interrupt
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It is serviced according to the flowchart in
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
The I bit of the CC register is set to prevent additional interrupts.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table
for vector addresses).
Figure
Figure
18.
18.
ST7LITEU05 ST7LITEU09