ST7FLITEU09M6TR STMicroelectronics, ST7FLITEU09M6TR Datasheet - Page 77

• Manufacturer Part Number: ST7FLITEU09M6TR
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: No

ST7LITEU05 ST7LITEU09
11.2.4
Table 29.
11.2.5
Table 30.
1. The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
2. Only if CK0=1 and CK1=0
11.2.6
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset
(RIM instruction).
Interrupt event
Overflow Event
CMP Event
Active-halt
Low power modes
Description of low power modes
Interrupts
Interrupt events
Register description
Timer control status register (ATCSR)
Reset value: 0000 0000 (00h)
Bits 7:5 = Reserved, must be kept cleared.
Bits 4:3 = CK[1:0] Counter Clock Selection.
Table 31.
Mode
Slow
Wait
Halt
These bits are set and cleared by software and cleared by hardware after a reset. They
select the clock frequency of the counter.
7
0
(1)
Counter clock selection
0
CMPFx
f
Event
LTIMER
OVF
flag
Counter clock selection
(1 ms timebase @ 8 MHz)
0
Reserved
AT timer halted except if CK0=1, CK1=0 and OVFIE=1
OFF
f
CPU
control
Enable
CMPIE
OVFIE
bit
CK1
The input frequency is divided by 32
Read/write
No effect on AT timer
AT timer halted
CK0
from
Wait
Exit
Yes
Yes
Description
OVF
from
Halt
Exit
No
No
On-chip peripherals
OVFIE
CK1
0
0
1
1
Active-halt
Yes
from
Exit
No
(2)
CMPIE
CK0
0
1
0
1
0
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